;ELC
;;; Compiled by mockbuild@buildfarm06-new.corp.cloudlinux.com on Fri Oct 11 10:09:31 2024
;;; from file /builddir/build/BUILD/emacs-24.3/lisp/progmodes/vhdl-mode.el
;;; in Emacs version 24.3.1
;;; with all optimizations.

;;; This file uses dynamic docstrings, first added in Emacs 19.29.

;;; This file does not contain utf-8 non-ASCII characters,
;;; and so can be loaded in Emacs versions earlier than 23.

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#@27 VHDL Mode version number.
(defconst vhdl-version "3.33.28" (#$ . 562))
#@39 VHDL Mode time stamp for last update.
(defconst vhdl-time-stamp "2010-09-22" (#$ . 639))
#@43 Non-nil if GNU Emacs 21, 22, ... is used.
(defconst vhdl-emacs-21 (byte-code "\301X\205\302\207" [emacs-major-version 21 t] 2) (#$ . 734))
#@39 Non-nil if GNU Emacs 22, ... is used.
(defconst vhdl-emacs-22 (byte-code "\301X\205\302\207" [emacs-major-version 22 t] 2) (#$ . 882))
#@73 Set variables as in `custom-set-default' and call FUNCTIONS afterwards.
(defalias 'vhdl-custom-set #[(variable value &rest functions) "\303\304!\203\304	\"\210\202\305	\"\210\n\205*\303\n@!\203\"\n@ \210\nA\211\204\306\207" [variable value functions fboundp custom-set-default set-default nil] 4 (#$ . 1026)])
#@93 Check that the value of WIDGET is a valid directory entry (i.e. ends with
'/' or is empty).
(defalias 'vhdl-widget-directory-validate #[(widget) "\302!\303\304	\"?\205\305\306\307#\210)\207" [widget val widget-value string-match "^\\(\\|.*/\\)$" widget-put :error "Invalid directory entry: must end with '/'"] 4 (#$ . 1353)])
(defconst vhdl-name-doc-string "\n\nFROM REGEXP is a regular expression matching the original name:\n  \".*\"       matches the entire string\n  \"\\(...\\)\"  matches a substring\nTO STRING specifies the string to be inserted as new name:\n  \"\\&\"  means substitute entire matched text\n  \"\\N\"  means substitute what matched the Nth \"\\(...\\)\"\nExamples:\n  \".*\"           \"\\&\"    inserts original string\n  \".*\"           \"\\&_i\"  attaches \"_i\" to original string\n  \"\\(.*\\)_[io]$\" \"\\1\"    strips off \"_i\" or \"_o\" from original string\n  \".*\"           \"foo\"   inserts constant string \"foo\"\n  \".*\"           \"\"      inserts empty string")
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\201
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\201

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\201
\201
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&\210\320\201
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\201
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\201)
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\314\201	
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\314\201I
&	\210\320\201]
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\201a
\323\201b
\332\201c
\314\201I
&	\210\320\201d
\201e
\201f
\323\201g
\332\201h
\314\201I
&	\210\320\201i
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&	\210\320\201l
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\323\201o
\332\201p
\314\201I
&	\210\306\201q
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\310\201t
\323\324\314\201q
&\210\320\201u
\201v
\201w
\323\201x
\314\201q
&\210\320\201y
\201z
\201{
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&\210\320\201
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\201\202
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\314\201q
&\210\320\201\205
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#\207" [vhdl-compiler-alist list alist x default-directory vhdl-project-alist custom-declare-group vhdl nil "Customizations for VHDL Mode." :prefix "vhdl-" :group languages vhdl-mode "Customizations for modes." custom-declare-variable vhdl-indent-tabs-mode "Non-nil means indentation can insert tabs.\nOverrides local variable `indent-tabs-mode'." :type boolean vhdl-compile "Customizations for compilation." '(("ADVance MS" "vacom" "-work \\1" "make" "-f \\1" nil "valib \\1; vamap \\2 \\1" "./" "work/" "Makefile" "adms" ("\\s-\\([0-9]+\\):" 0 1 0) ("Compiling file \\(.+\\)" 1) ("ENTI/\\1.vif" "ARCH/\\1-\\2.vif" "CONF/\\1.vif" "PACK/\\1.vif" "BODY/\\1.vif" upcase)) ("Aldec" "vcom" "-93 -work \\1" "make" "-f \\1" nil "vlib \\1; vmap \\2 \\1" "./" "work/" "Makefile" "aldec" (".+?[ 	]+\\(?:ERROR\\)[^:]+:.+?\\(?:.+\"\\(.+?\\)\"[ 	]+\\([0-9]+\\)\\)" 1 2 0) (#1="" 0) nil) ("Cadence Leapfrog" "cv" "-work \\1 -file" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "leapfrog" ("duluth: \\*E,[0-9]+ (\\(.+\\),\\([0-9]+\\)):" 1 2 0) (#1# 0) ("\\1/entity" "\\2/\\1" "\\1/configuration" "\\1/package" "\\1/body" downcase)) ("Cadence NC" "ncvhdl" "-work \\1" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "ncvhdl" ("ncvhdl_p: \\*E,\\w+ (\\(.+\\),\\([0-9]+\\)|\\([0-9]+\\)):" 1 2 3) (#1# 0) ("\\1/entity/pc.db" "\\2/\\1/pc.db" "\\1/configuration/pc.db" "\\1/package/pc.db" "\\1/body/pc.db" downcase)) ("GHDL" "ghdl" "-i --workdir=\\1 --ieee=synopsys -fexplicit " "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "ghdl" ("ghdl_p: \\*E,\\w+ (\\(.+\\),\\([0-9]+\\)|\\([0-9]+\\)):" 1 2 3) (#1# 0) ("\\1/entity" "\\2/\\1" "\\1/configuration" "\\1/package" "\\1/body" downcase)) ("Ikos" "analyze" "-l \\1" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "ikos" ("E L\\([0-9]+\\)/C\\([0-9]+\\):" 0 1 2) ("^analyze +\\(.+ +\\)*\\(.+\\)$" 2) nil) ("ModelSim" "vcom" "-93 -work \\1" "make" "-f \\1" nil "vlib \\1; vmap \\2 \\1" "./" "work/" "Makefile" "modelsim" ("\\(ERROR\\|WARNING\\|\\*\\* Error\\|\\*\\* Warning\\)[^:]*:\\( *[[0-9]+]\\)? \\(.+\\)(\\([0-9]+\\)):" 3 4 0) (#1# 0) ("\\1/_primary.dat" "\\2/\\1.dat" "\\1/_primary.dat" "\\1/_primary.dat" "\\1/body.dat" downcase)) ("LEDA ProVHDL" "provhdl" "-w \\1 -f" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "provhdl" ("\\([^ 	\n]+\\):\\([0-9]+\\): " 1 2 0) (#1# 0) ("ENTI/\\1.vif" "ARCH/\\1-\\2.vif" "CONF/\\1.vif" "PACK/\\1.vif" "BODY/BODY-\\1.vif" upcase)) ("QuickHDL" "qvhcom" "-work \\1" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "quickhdl" ("\\(ERROR\\|WARNING\\)[^:]*: \\(.+\\)(\\([0-9]+\\)):" 2 3 0) (#1# 0) ("\\1/_primary.dat" "\\2/\\1.dat" "\\1/_primary.dat" "\\1/_primary.dat" "\\1/body.dat" downcase)) ("Savant" "scram" "-publish-cc -design-library-name \\1" "make" "-f \\1" nil "mkdir \\1" "./" "work._savant_lib/" "Makefile" "savant" ("\\([^ 	\n]+\\):\\([0-9]+\\): " 1 2 0) (#1# 0) ("\\1_entity.vhdl" "\\2_secondary_units._savant_lib/\\2_\\1.vhdl" "\\1_config.vhdl" "\\1_package.vhdl" "\\1_secondary_units._savant_lib/\\1_package_body.vhdl" downcase)) ("Simili" "vhdlp" "-work \\1" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "simili" ("\\(Error\\|Warning\\): \\w+: \\(.+\\): (line \\([0-9]+\\)): " 2 3 0) (#1# 0) ("\\1/prim.var" "\\2/_\\1.var" "\\1/prim.var" "\\1/prim.var" "\\1/_body.var" downcase)) ("Speedwave" "analyze" "-libfile vsslib.ini -src" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "speedwave" ("^ *ERROR[[0-9]+]::File \\(.+\\) Line \\([0-9]+\\):" 1 2 0) (#1# 0) nil) ("Synopsys" "vhdlan" "-nc -work \\1" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "synopsys" ("\\*\\*Error: vhdlan,[0-9]+ \\(.+\\)(\\([0-9]+\\)):" 1 2 0) (#1# 0) ("\\1.sim" "\\2__\\1.sim" "\\1.sim" "\\1.sim" "\\1__.sim" upcase)) ("Synopsys Design Compiler" "vhdlan" "-nc -spc -work \\1" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "synopsys_dc" ("\\*\\*Error: vhdlan,[0-9]+ \\(.+\\)(\\([0-9]+\\)):" 1 2 0) (#1# 0) ("\\1.syn" "\\2__\\1.syn" "\\1.syn" "\\1.syn" "\\1__.syn" upcase)) ("Synplify" "n/a" "n/a" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "synplify" ("@[EWN]:\"\\(.+\\)\":\\([0-9]+\\):\\([0-9]+\\):" 1 2 3) (#1# 0) nil) ("Vantage" "analyze" "-libfile vsslib.ini -src" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "vantage" ("\\*\\*Error: LINE \\([0-9]+\\) \\*\\*\\*" 0 1 0) ("^ *Compiling \"\\(.+\\)\" " 1) nil) ("VeriBest" "vc" "vhdl" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "veribest" ("^ +\\([0-9]+\\): +[^ ]" 0 1 0) (#1# 0) nil) ("Viewlogic" "analyze" "-libfile vsslib.ini -src" "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "viewlogic" ("\\*\\*Error: LINE \\([0-9]+\\) \\*\\*\\*" 0 1 0) ("^ *Compiling \"\\(.+\\)\" " 1) nil) ("Xilinx XST" "xflow" #1# "make" "-f \\1" nil "mkdir \\1" "./" "work/" "Makefile" "xilinx" ("^ERROR:HDLParsers:[0-9]+ - \"\\(.+\\)\" Line \\([0-9]+\\)." 1 2 0) (#1# 0) nil)) "List of available VHDL compilers and their properties.\nEach list entry specifies the following items for a compiler:\nCompiler:\n  Compiler name    : name used in option `vhdl-compiler' to choose compiler\n  Compile command  : command used for source file compilation\n  Compile options  : compile options (\"\\1\" inserts library name)\n  Make command     : command used for compilation using a Makefile\n  Make options     : make options (\"\\1\" inserts Makefile name)\n  Generate Makefile: use built-in function or command to generate a Makefile\n                     (\"\\1\" inserts Makefile name, \"\\2\" inserts library name)\n  Library command  : command to create library directory (\"\\1\" inserts\n                     library directory, \"\\2\" inserts library name)\n  Compile directory: where compilation is run and the Makefile is placed\n  Library directory: directory of default library\n  Makefile name    : name of Makefile (default is \"Makefile\")\n  ID string        : compiler identification string (see `vhdl-project-alist')\nError message:\n  Regexp           : regular expression to match error messages (*)\n  File subexp index: index of subexpression that matches the file name\n  Line subexp index: index of subexpression that matches the line number\n  Column subexp idx: index of subexpression that matches the column number\nFile message:\n  Regexp           : regular expression to match a file name message\n  File subexp index: index of subexpression that matches the file name\nUnit-to-file name mapping: mapping of library unit names to names of files\n                     generated by the compiler (used for Makefile generation)\n  To string        : string a name is mapped to (\"\\1\" inserts the unit name,\n                     \"\\2\" inserts the entity name for architectures)\n  Case adjustment  : adjust case of inserted unit names\n\n(*) The regular expression must match the error message starting from the\n    beginning of the line (but not necessarily to the end of the line).\n\nCompile options allows insertion of the library name (see `vhdl-project-alist')\nin order to set the compilers library option (e.g. \"vcom -work my_lib\").\n\nFor Makefile generation, the built-in function can be used (requires\nspecification of the unit-to-file name mapping).  Alternatively, an\nexternal command can be specified.  Work directory allows specification of\nan alternative \"work\" library path (e.g. \"WORK/\" instead of \"work/\",\nused for Makefile generation).  To use another library name than \"work\",\ncustomize `vhdl-project-alist'.  The library command is inserted in Makefiles\nto automatically create the library directory if not existent.\n\nCompile options, compile directory, library directory, and Makefile name are\noverwritten by the project settings if a project is defined (see\n`vhdl-project-alist').  Directory paths are relative to the source file\ndirectory.\n\nSome compilers do not include the file name in the error message, but print\nout a file name message in advance.  In this case, set \"File Subexp Index\"\nunder \"Error Message\" to 0 and fill out the \"File Message\" entries.\nIf no file name at all is printed out, set both \"File Message\" entries to 0\n(a default file name message will be printed out instead, does not work in\nXEmacs).\n\nA compiler is selected for syntax analysis (`\\[vhdl-compile]') by\nassigning its name to option `vhdl-compiler'.\n\nPlease send any missing or erroneous compiler properties to the maintainer for\nupdating.\n\nNOTE: Activate new error and file message regexps and reflect the new setting\n      in the choice list of option `vhdl-compiler' by restarting Emacs." (repeat (list :tag "Compiler" :indent 2 (string :tag "Compiler name      ") (string :tag "Compile command    ") (string :tag "Compile options    " "-work \\1") (string :tag "Make command       " "make") (string :tag "Make options       " "-f \\1") (choice :tag "Generate Makefile  " (const :tag "Built-in function" nil) (string :tag "Command" "vmake \\2 > \\1")) (string :tag "Library command    " "mkdir \\1") (directory :tag "Compile directory  " :validate vhdl-widget-directory-validate "./") (directory :tag "Library directory  " :validate vhdl-widget-directory-validate "work/") (file :tag "Makefile name      " "Makefile") (string :tag "ID string          ") (list :tag "Error message" :indent 4 (regexp :tag "Regexp           ") (integer :tag "File subexp index") (integer :tag "Line subexp index") (integer :tag "Column subexp idx")) (list :tag "File message" :indent 4 (regexp :tag "Regexp           ") (integer :tag "File subexp index")) (choice :tag "Unit-to-file name mapping" :format "%t: %[Value Menu%] %v\n" (const :tag "Not defined" nil) (list :tag "To string" :indent 4 (string :tag "Entity           " "\\1.vhd") (string :tag "Architecture     " "\\2_\\1.vhd") (string :tag "Configuration    " "\\1.vhd") (string :tag "Package          " "\\1.vhd") (string :tag "Package Body     " "\\1_body.vhd") (choice :tag "Case adjustment  " (const :tag "None" identity) (const :tag "Upcase" upcase) (const :tag "Downcase" downcase)))))) :set #[(variable value) "\302	\303#\207" [variable value vhdl-custom-set vhdl-update-mode-menu] 4] vhdl-compiler "GHDL" "Specifies the VHDL compiler to be used for syntax analysis.\nSelect a compiler name from the ones defined in option `vhdl-compiler-alist'." const append (choice) vhdl-compile-use-local-error-regexp t "Non-nil means use buffer-local `compilation-error-regexp-alist'.\nIn this case, only error message regexps for VHDL compilers are active if\ncompilation is started from a VHDL buffer.  Otherwise, the error message\nregexps are appended to the predefined global regexps, and all regexps are\nactive all the time.  Note that by doing that, the predefined global regexps\nmight result in erroneous parsing of error messages for some VHDL compilers.\n\nNOTE: Activate the new setting by restarting Emacs." vhdl-makefile-default-targets '("all" "clean" "library") "List of default target names in Makefiles.\nAutomatically generated Makefiles include three default targets to compile\nthe entire design, clean the entire design and to create the design library.\nThis option allows to change the names of these targets to avoid conflicts\nwith other user Makefiles." (list (string :tag "Compile entire design") (string :tag "Clean entire design  ") (string :tag "Create design library")) :version "24.3" vhdl-makefile-generation-hook "Functions to run at the end of Makefile generation.\nAllows to insert user specific parts into a Makefile.\n\nExample:\n  (lambda nil\n    (re-search-backward \"^# Rule for compiling entire design\")\n    (insert \"# My target\\n\\n.MY_TARGET :\\n\\n\\n\"))" hook vhdl-default-library "work" "Name of default library.\nIs overwritten by project settings if a project is active." string vhdl-project "Customizations for projects." '(("Example 1" "Source files in two directories, custom library name, VHDL'87" "~/example1/" ("src/system/" "src/components/") #1# (("ModelSim" "-87 \\2" "-f \\1 top_level" nil) ("Synopsys" "-vhdl87 \\2" "-f \\1 top_level" ((".*/datapath/.*" . "-optimize \\3") (".*_tb\\.vhd")))) "lib/" "example3_lib" "lib/example3/" "Makefile_\\2" #1#) ("Example 2" "Individual source files, multiple compilers in different directories" "$EXAMPLE2/" ("vhdl/system.vhd" "vhdl/component_*.vhd") #1# nil "\\1/" "work" "\\1/work/" "Makefile" #1#) ("Example 3" "Source files in a directory tree, multiple compilers in same directory" "/home/me/example3/" ("-r ./*/vhdl/") "/CVS/" nil "./" "work" "work-\\1/" "Makefile-\\1" "-------------------------------------------------------------------------------\n-- This is a multi-line project description\n-- that can be used as a project dependent part of the file header.\n")) "List of projects and their properties.\n  Name             : name used in option `vhdl-project' to choose project\n  Title            : title of project (single-line string)\n  Default directory: default project directory (absolute path)\n  Sources          : a) source files  : path + \"/\" + file name\n                     b) directory     : path + \"/\"\n                     c) directory tree: \"-r \" + path + \"/\"\n  Exclude regexp   : matches file/directory names to be excluded as sources\n  Compile options  : project-specific options for each compiler\n    Compiler name  : name of compiler for which these options are valid\n    Compile options: project-specific compiler options\n                     (\"\\1\" inserts library name, \"\\2\" default options)\n    Make options:    project-specific make options\n                     (\"\\1\" inserts Makefile name, \"\\2\" default options)\n    Exceptions     : file-specific exceptions\n      File name regexp: matches file names for which exceptions are valid\n      - Options       : file-specific compiler options string\n                        (\"\\1\" inserts library name, \"\\2\" default options,\n                        \"\\3\" project-specific options)\n      - Do not compile: do not compile this file (in Makefile)\n  Compile directory: where compilation is run and the Makefile is placed\n                     (\"\\1\" inserts compiler ID string)\n  Library name     : name of library (default is \"work\")\n  Library directory: path to library (\"\\1\" inserts compiler ID string)\n  Makefile name    : name of Makefile\n                     (\"\\1\" inserts compiler ID string, \"\\2\" library name)\n  Description      : description of project (multi-line string)\n\nProject title and description are used to insert into the file header (see\noption `vhdl-file-header').\n\nThe default directory must have an absolute path (use `M-TAB' for completion).\nAll other paths can be absolute or relative to the default directory.  All\npaths must end with '/'.\n\nThe design units found in the sources (files and directories) are shown in the\nhierarchy browser.  Path and file name can contain wildcards `*' and `?' as\nwell as \"./\" and \"../\" (\"sh\" syntax).  Paths can also be absolute.\nEnvironment variables (e.g. \"$EXAMPLE2\") are resolved.  If no sources are\nspecified, the default directory is taken as source directory.  Otherwise,\nthe default directory is only taken as source directory if there is a sources\nentry with the empty string or \"./\".  Exclude regexp allows to filter out\nspecific file and directory names from the list of sources (e.g. CVS\ndirectories).\n\nFiles are compiled in the compile directory.  Makefiles are also placed into\nthe compile directory.  Library directory specifies which directory the\ncompiler compiles into (used to generate the Makefile).\n\nSince different compile/library directories and Makefiles may exist for\ndifferent compilers within one project, these paths and names allow the\ninsertion of a compiler-dependent ID string (defined in `vhdl-compiler-alist').\nCompile options, compile directory, library directory, and Makefile name\noverwrite the settings of the current compiler.\n\nFile-specific compiler options (highest priority) overwrite project-specific\noptions which overwrite default options (lowest priority).  Lower priority\noptions can be inserted in higher priority options.  This allows to reuse\ndefault options (e.g. \"-file\") in project- or file-specific options (e.g.\n\"-93 -file\").\n\nNOTE: Reflect the new setting in the choice list of option `vhdl-project'\n      by restarting Emacs." repeat :tag "Project" :indent 2 (string :tag "Name             ") (string :tag "Title            ") directory "Default directory" :validate vhdl-name-doc-string vhdl-widget-directory-validate abbreviate-file-name (repeat :tag "Sources          " :indent 4 (directory :format "     %v" "./")) (regexp :tag "Exclude regexp   ") "Compile options  " 4 "Compiler" 6 (choice :tag "Compiler name") ((string :tag "Compile options" "\\2") (string :tag "Make options   " "\\2") (repeat :tag "Exceptions   " :indent 8 (cons :format "%v" (regexp :tag "File name regexp    ") (choice :format "%[Value Menu%] %v" (string :tag "Options" "\\3") (const :tag "Do not compile" nil))))) ((directory :tag "Compile directory" :validate vhdl-widget-directory-validate "./") (string :tag "Library name     " "work") (directory :tag "Library directory" :validate vhdl-widget-directory-validate "work/") (file :tag "Makefile name    " "Makefile") (string :tag "Description: (type `C-j' for newline)" :format "%t\n%v\n")) #[(variable value) "\302	\303\304$\207" [variable value vhdl-custom-set vhdl-update-mode-menu vhdl-speedbar-refresh] 5] "Specifies the default for the current project.\nSelect a project name from the ones defined in option `vhdl-project-alist'.\nIs used to determine the project title and description to be inserted in file\nheaders and the source files/directories to be scanned in the hierarchy\nbrowser.  The current project can also be changed temporarily in the menu." (choice (const :tag "None" nil) (const :tag "--")) vhdl-project-file-name '("\\1.prj") "List of file names/paths for importing/exporting project setups.\n\"\\1\" is replaced by the project name (SPC is replaced by `_'), \"\\2\" is\nreplaced by the user name (allows to have user-specific project setups).\nThe first entry is used as file name to import/export individual project\nsetups.  All entries are used to automatically import project setups at\nstartup (see option `vhdl-project-auto-load').  Projects loaded from the\nfirst entry are automatically made current.  Hint: specify local project\nsetups in first entry, global setups in following entries; loading a local\nproject setup will make it current, while loading the global setups\nis done without changing the current project.\nNames can also have an absolute path (i.e. project setups can be stored\nin global directories)." (repeat (string :tag "File name" "\\1.prj")) vhdl-project-auto-load '(startup) "Automatically load project setups from files.\nAll project setup files that match the file names specified in option\n`vhdl-project-file-name' are automatically loaded.  The project of the\n(alphabetically) last loaded setup of the first `vhdl-project-file-name'\nentry is activated.\nA project setup file can be obtained by exporting a project (see menu).\n  At startup: project setup file is loaded at Emacs startup" (set (const :tag "At startup" startup)) vhdl-project-sort "Non-nil means projects are displayed in alphabetical order." vhdl-style "Customizations for coding styles." vhdl-template vhdl-port vhdl-compose vhdl-standard '(93 nil) "VHDL standards used.\nBasic standard:\n  VHDL'87      : IEEE Std 1076-1987\n  VHDL'93/02   : IEEE Std 1076-1993/2002\nAdditional standards:\n  VHDL-AMS     : IEEE Std 1076.1 (analog-mixed-signal)\n  Math packages: IEEE Std 1076.2 (`math_real', `math_complex')\n\nNOTE: Activate the new setting in a VHDL buffer by using the menu entry\n      \"Activate Options\"." (list (choice :tag "Basic standard" (const :tag "VHDL'87" 87) (const :tag "VHDL'93/02" 93)) (set :tag "Additional standards" :indent 2 (const :tag "VHDL-AMS" ams) (const :tag "Math packages" math))) #[(variable value) "\302	\303\304\305\306\307\310\311&	\207" [variable value vhdl-custom-set vhdl-template-map-init vhdl-mode-abbrev-table-init vhdl-template-construct-alist-init vhdl-template-package-alist-init vhdl-update-mode-menu vhdl-words-init vhdl-font-lock-init] 10] vhdl-basic-offset "Amount of basic offset used for indentation.\nThis value is used by + and - symbols in `vhdl-offsets-alist'." integer vhdl-upper-case-keywords "Non-nil means convert keywords to upper case.\nThis is done when typed or expanded or by the fix case functions." #[(variable value) "\302	\303#\207" [variable value vhdl-custom-set vhdl-abbrev-list-init] 4] vhdl-upper-case-types "Non-nil means convert standardized types to upper case.\nThis is done when expanded or by the fix case functions." #[(variable value) "\302	\303#\207" [variable value vhdl-custom-set vhdl-abbrev-list-init] 4] vhdl-upper-case-attributes "Non-nil means convert standardized attributes to upper case.\nThis is done when expanded or by the fix case functions." #[(variable value) "\302	\303#\207" [variable value vhdl-custom-set vhdl-abbrev-list-init] 4] vhdl-upper-case-enum-values "Non-nil means convert standardized enumeration values to upper case.\nThis is done when expanded or by the fix case functions." #[(variable value) "\302	\303#\207" [variable value vhdl-custom-set vhdl-abbrev-list-init] 4] vhdl-upper-case-constants "Non-nil means convert standardized constants to upper case.\nThis is done when expanded." #[(variable value) "\302	\303#\207" [variable value vhdl-custom-set vhdl-abbrev-list-init] 4] vhdl-use-direct-instantiation 'standard "Non-nil means use VHDL'93 direct component instantiation.\n  Never   : never\n  Standard: only in VHDL standards that allow it (VHDL'93 and higher)\n  Always  : always" (choice (const :tag "Never" never) (const :tag "Standard" standard) (const :tag "Always" always)) vhdl-array-index-record-field-in-sensitivity-list "Non-nil means include array indices / record fields in sensitivity list.\nIf a signal read in a process is a record field or pointed to by an array\nindex, the record field or array index is included with the record name in\nthe sensitivity list (e.g. \"in1(0)\", \"in2.f0\").\nOtherwise, only the record name is included (e.g. \"in1\", \"in2\")." vhdl-naming "Customizations for naming conventions." vhdl-entity-file-name '(".*" . "\\&") "Specifies how the entity file name is obtained.\nThe entity file name can be obtained by modifying the entity name (e.g.\nattaching or stripping off a substring).  The file extension is automatically\ntaken from the file name of the current buffer." (cons (regexp :tag "From regexp") (string :tag "To string  ")) vhdl-architecture-file-name '("\\(.*\\) \\(.*\\)" . "\\1_\\2") "Specifies how the architecture file name is obtained.\nThe architecture file name can be obtained by modifying the entity\nand/or architecture name (e.g. attaching or stripping off a substring).  The\nfile extension is automatically taken from the file name of the current\nbuffer.  The string that is matched against the regexp is the concatenation\nof the entity and the architecture name separated by a space.  This gives\naccess to both names (see default setting as example)." (cons (regexp :tag "From regexp") (string :tag "To string  ")) vhdl-configuration-file-name '(".*" . "\\&") "Specifies how the configuration file name is obtained.\nThe configuration file name can be obtained by modifying the configuration\nname (e.g. attaching or stripping off a substring).  The file extension is\nautomatically taken from the file name of the current buffer." (cons (regexp :tag "From regexp") (string :tag "To string  ")) vhdl-package-file-name '(".*" . "\\&") "Specifies how the package file name is obtained.\nThe package file name can be obtained by modifying the package name (e.g.\nattaching or stripping off a substring).  The file extension is automatically\ntaken from the file name of the current buffer.  Package files can be created\nin a different directory by prepending a relative or absolute path to the\nfile name." (cons (regexp :tag "From regexp") (string :tag "To string  ")) vhdl-file-name-case 'identity "Specifies how to change case for obtaining file names.\nWhen deriving a file name from a VHDL unit name, case can be changed as\nfollows:\n  As Is:      case is not changed (taken as is)\n  Lower Case: whole name is changed to lower case\n  Upper Case: whole name is changed to upper case\n  Capitalize: first letter of each word in name is capitalized" (choice (const :tag "As Is" identity) (const :tag "Lower Case" downcase) (const :tag "Upper Case" upcase) (const :tag "Capitalize" capitalize)) "Customizations for electrification." vhdl-electric-keywords '(vhdl user) "Type of keywords for which electrification is enabled.\n  VHDL keywords: invoke built-in templates\n  User keywords: invoke user models (see option `vhdl-model-alist')" (set (const :tag "VHDL keywords" vhdl) (const :tag "User model keywords" user)) #[(variable value) "\302	\303#\207" [variable value vhdl-custom-set vhdl-mode-abbrev-table-init] 4] vhdl-optional-labels 'process "Constructs for which labels are to be queried.\nTemplate generators prompt for optional labels for:\n  None          : no constructs\n  Processes only: processes only (also procedurals in VHDL-AMS)\n  All constructs: all constructs with optional labels and keyword END" (choice (const :tag "None" none) (const :tag "Processes only" process) (const :tag "All constructs" all)) vhdl-insert-empty-lines 'unit "Specifies whether to insert empty lines in some templates.\nThis improves readability of code.  Empty lines are inserted in:\n  None             : no constructs\n  Design units only: entities, architectures, configurations, packages only\n  All constructs   : also all constructs with BEGIN...END parts\n\nReplaces option `vhdl-additional-empty-lines'." (choice (const :tag "None" none) (const :tag "Design units only" unit) (const :tag "All constructs" all)) vhdl-argument-list-indent "Non-nil means indent argument lists relative to opening parenthesis.\nThat is, argument, association, and port lists start on the same line as the\nopening parenthesis and subsequent lines are indented accordingly.\nOtherwise, lists start on a new line and are indented as normal code." vhdl-association-list-with-formals "Non-nil means write association lists with formal parameters.\nTemplates prompt for formal and actual parameters (ports/generics).\nWhen pasting component instantiations, formals are included.\nIf nil, only a list of actual parameters is entered." vhdl-conditions-in-parenthesis "Non-nil means place parenthesis around condition expressions." vhdl-zero-string "'0'" "String to use for a logic zero." vhdl-one-string "'1'" "String to use for a logic one." vhdl-header "Customizations for file header." vhdl-file-header "-------------------------------------------------------------------------------\n-- Title      : <title string>\n-- Project    : <project>\n-------------------------------------------------------------------------------\n-- File       : <filename>\n-- Author     : <author>\n-- Company    : <company>\n-- Created    : <date>\n-- Last update: <date>\n-- Platform   : <platform>\n-- Standard   : <standard>\n<projectdesc>-------------------------------------------------------------------------------\n-- Description: <cursor>\n<copyright>-------------------------------------------------------------------------------\n-- Revisions  :\n-- Date        Version  Author  Description\n-- <date>  1.0      <login>	Created\n-------------------------------------------------------------------------------\n\n" "String or file to insert as file header.\nIf the string specifies an existing file name, the contents of the file is\ninserted, otherwise the string itself is inserted as file header.\nType `C-j' for newlines.\nIf the header contains RCS keywords, they may be written as <RCS>Keyword<RCS>\nif the header needs to be version controlled.\n\nThe following keywords for template generation are supported:\n  <filename>    : replaced by the name of the buffer\n  <author>      : replaced by the user name and email address\n                  (`user-full-name',`mail-host-address', `user-mail-address')\n  <authorfull>  : replaced by the user full name (`user-full-name')\n  <login>       : replaced by user login name (`user-login-name')\n  <company>     : replaced by contents of option `vhdl-company-name'\n  <date>        : replaced by the current date\n  <year>        : replaced by the current year\n  <project>     : replaced by title of current project (`vhdl-project')\n  <projectdesc> : replaced by description of current project (`vhdl-project')\n  <copyright>   : replaced by copyright string (`vhdl-copyright-string')\n  <platform>    : replaced by contents of option `vhdl-platform-spec'\n  <standard>    : replaced by the VHDL language standard(s) used\n  <... string>  : replaced by a queried string (\"...\" is the prompt word)\n  <title string>: replaced by file title in automatically generated files\n  <cursor>      : final cursor position\n\nThe (multi-line) project description <projectdesc> can be used as a project\ndependent part of the file header and can also contain the above keywords." vhdl-file-footer #1# "String or file to insert as file footer.\nIf the string specifies an existing file name, the contents of the file is\ninserted, otherwise the string itself is inserted as file footer (i.e. at\nthe end of the file).\nType `C-j' for newlines.\nThe same keywords as in option `vhdl-file-header' can be used." vhdl-company-name "Name of company to insert in file header.\nSee option `vhdl-file-header'." vhdl-copyright-string "-------------------------------------------------------------------------------\n-- Copyright (c) <year> <company>\n" "Copyright string to insert in file header.\nCan be multi-line string (type `C-j' for newline) and contain other file\nheader keywords (see option `vhdl-file-header')." vhdl-platform-spec "Specification of VHDL platform to insert in file header.\nThe platform specification should contain names and versions of the\nsimulation and synthesis tools used.\nSee option `vhdl-file-header'." vhdl-date-format "%Y-%m-%d" "Specifies the date format to use in the header.\nThis string is passed as argument to the command `format-time-string'.\nFor more information on format strings, see the documentation for the\n`format-time-string' command (C-h f `format-time-string')." vhdl-modify-date-prefix-string "-- Last update: " "Prefix string of modification date in VHDL file header.\nIf actualization of the modification date is called (menu,\n`\\[vhdl-template-modify]'), this string is searched and the rest\nof the line replaced by the current date." vhdl-modify-date-on-saving "Non-nil means update the modification date when the buffer is saved.\nCalls function `\\[vhdl-template-modify]').\n\nNOTE: Activate the new setting in a VHDL buffer by using the menu entry\n      \"Activate Options\"." vhdl-sequential-process "Customizations for sequential processes." vhdl-reset-kind 'async "Specifies which kind of reset to use in sequential processes." (choice (const :tag "None" none) (const :tag "Synchronous" sync) (const :tag "Asynchronous" async) (const :tag "Query" query)) vhdl-reset-active-high "Non-nil means reset in sequential processes is active high.\nOtherwise, reset is active low." vhdl-clock-rising-edge "Non-nil means rising edge of clock triggers sequential processes.\nOtherwise, falling edge triggers." vhdl-clock-edge-condition 'standard "Syntax of the clock edge condition.\n  Standard: \"clk'event and clk = '1'\"\n  Function: \"rising_edge(clk)\"" (choice (const :tag "Standard" standard) (const :tag "Function" function)) vhdl-clock-name "Name of clock signal to use in templates." vhdl-reset-name "Name of reset signal to use in templates." vhdl-model "Customizations for user models." vhdl-model-alist '(("Example Model" "<label> : process (<clock>, <reset>)\nbegin  -- process <label>\n  if <reset> = '0' then  -- asynchronous reset (active low)\n    <cursor>\n  elsif <clock>'event and <clock> = '1' then  -- rising clock edge\n    if <enable> = '1' then  -- synchronous load\n\n    end if;\n  end if;\nend process <label>;" "e" #1#)) "List of user models.\nVHDL models (templates) can be specified by the user in this list.  They can be\ninvoked from the menu, through key bindings (`C-c C-m ...'), or by keyword\nelectrification (i.e. overriding existing or creating new keywords, see\noption `vhdl-electric-keywords').\n  Name       : name of model (string of words and spaces)\n  String     : string or name of file to be inserted as model (newline: `C-j')\n  Key Binding: key binding to invoke model, added to prefix `C-c C-m'\n                (must be in double-quotes, examples: \"i\", \"\\C-p\", \"\\M-s\")\n  Keyword    : keyword to invoke model\n\nThe models can contain prompts to be queried.  A prompt is of the form \"<...>\".\nA prompt that appears several times is queried once and replaced throughout\nthe model.  Special prompts are:\n  <clock> : name specified in `vhdl-clock-name' (if not empty)\n  <reset> : name specified in `vhdl-reset-name' (if not empty)\n  <cursor>: final cursor position\nFile header prompts (see variable `vhdl-file-header') are automatically\nreplaced, so that user models can also be used to insert different types of\nheaders.\n\nIf the string specifies an existing file name, the contents of the file is\ninserted, otherwise the string itself is inserted.\nThe code within the models should be correctly indented.\nType `C-j' for newlines.\n\nNOTE: Activate the new setting in a VHDL buffer by using the menu entry\n      \"Activate Options\"." (repeat (list :tag "Model" :indent 2 (string :tag "Name       ") (string :tag "String     : (type `C-j' for newline)" :format "%t\n%v") (sexp :tag "Key binding" x) (string :tag "Keyword    " :format "%t: %v\n"))) #[(variable value) "\302	\303\304\305\306&\207" [variable value vhdl-custom-set vhdl-model-map-init vhdl-model-defun vhdl-mode-abbrev-table-init vhdl-update-mode-menu] 7] "Customizations for structural composition." vhdl-compose-architecture-name '(".*" . "str") "Specifies how the component architecture name is obtained.\nThe component architecture name can be obtained by modifying the entity name\n(e.g. attaching or stripping off a substring).\nIf TO STRING is empty, the architecture name is queried." (cons (regexp :tag "From regexp") (string :tag "To string  ")) vhdl-compose-configuration-name '("\\(.*\\) \\(.*\\)" . "\\1_\\2_cfg") "Specifies how the configuration name is obtained.\nThe configuration name can be obtained by modifying the entity and/or\narchitecture name (e.g. attaching or stripping off a substring).  The string\nthat is matched against the regexp is the concatenation of the entity and the\narchitecture name separated by a space.  This gives access to both names (see\ndefault setting as example)." (cons (regexp :tag "From regexp") (string :tag "To string  ")) vhdl-components-package-name '((".*" . "\\&_components") . "components") "Specifies how the name for the components package is obtained.\nThe components package is a package containing all component declarations for\nthe current design.  Its name can be obtained by modifying the project name\n(e.g. attaching or stripping off a substring).  If no project is defined, the\nDIRECTORY entry is chosen." (cons (cons :tag "Project" :indent 2 (regexp :tag "From regexp") (string :tag "To string  ")) (string :tag "Directory:\n  String     ")) vhdl-use-components-package "Non-nil means use a separate components package for component declarations.\nOtherwise, component declarations are inserted and searched for in the\narchitecture declarative parts." vhdl-compose-include-header "Non-nil means include a header in automatically generated files." vhdl-compose-create-files 'single "Specifies whether new files should be created for the new component.\nThe component's entity and architecture are inserted:\n  None          : in current buffer\n  Single file   : in new single file\n  Separate files: in two separate files\nThe file names are obtained from variables `vhdl-entity-file-name' and\n`vhdl-architecture-file-name'." (choice (const :tag "None" none) (const :tag "Single file" single) (const :tag "Separate files" separate)) vhdl-compose-configuration-create-file "Specifies whether a new file should be created for the configuration.\nIf non-nil, a new file is created for the configuration.\nThe file name is obtained from variable `vhdl-configuration-file-name'." vhdl-compose-configuration-hierarchical "Specifies whether hierarchical configurations should be created.\nIf non-nil, automatically created configurations are hierarchical and include\nthe whole hierarchy of subcomponents.  Otherwise the configuration only\nincludes one level of subcomponents." vhdl-compose-configuration-use-subconfiguration "Specifies whether subconfigurations should be used inside configurations.\nIf non-nil, automatically created configurations use configurations in binding\nindications for subcomponents, if such configurations exist.  Otherwise,\nentities are used in binding indications for subcomponents." "Customizations for port translation functions." vhdl-include-port-comments "Non-nil means include port comments when a port is pasted." vhdl-include-direction-comments "Non-nil means include port direction in instantiations as comments." vhdl-include-type-comments "Non-nil means include generic/port type in instantiations as comments." vhdl-include-group-comments 'never "Specifies whether to include group comments and spacings.\nThe comments and empty lines between groups of ports are pasted:\n  Never       : never\n  Declarations: in entity/component/constant/signal declarations only\n  Always      : also in generic/port maps" (choice (const :tag "Never" never) (const :tag "Declarations" decl) (const :tag "Always" always)) vhdl-actual-port-name '(".*" . "\\&") "Specifies how actual port names are obtained from formal port names.\nIn a component instantiation, an actual port name can be obtained by\nmodifying the formal port name (e.g. attaching or stripping off a substring)." (cons (regexp :tag "From regexp") (string :tag "To string  ")) vhdl-instance-name '(".*" . "\\&_%d") "Specifies how an instance name is obtained.\nThe instance name can be obtained by modifying the name of the component to be\ninstantiated (e.g. attaching or stripping off a substring).  \"%d\" is replaced\nby a unique number (starting with 1).\nIf TO STRING is empty, the instance name is queried." (cons (regexp :tag "From regexp") (string :tag "To string  ")) vhdl-testbench "Customizations for testbench generation." vhdl-testbench-entity-name '(".*" . "\\&_tb") "Specifies how the testbench entity name is obtained.\nThe entity name of a testbench can be obtained by modifying the name of\nthe component to be tested (e.g. attaching or stripping off a substring)." (cons (regexp :tag "From regexp") (string :tag "To string  ")) vhdl-testbench-architecture-name '(".*" . #1#) "Specifies how the testbench architecture name is obtained.\nThe testbench architecture name can be obtained by modifying the name of\nthe component to be tested (e.g. attaching or stripping off a substring).\nIf TO STRING is empty, the architecture name is queried." (cons (regexp :tag "From regexp") (string :tag "To string  ")) vhdl-testbench-configuration-name "Specifies how the testbench configuration name is obtained.\nThe configuration name of a testbench can be obtained by modifying the entity\nand/or architecture name (e.g. attaching or stripping off a substring).  The\nstring that is matched against the regexp is the concatenation of the entity\nand the architecture name separated by a space.  This gives access to both\nnames (see default setting as example)." (cons (regexp :tag "From regexp") (string :tag "To string  ")) vhdl-testbench-dut-name '(".*" . "DUT") "Specifies how a DUT instance name is obtained.\nThe design-under-test instance name (i.e. the component instantiated in the\ntestbench) can be obtained by modifying the component name (e.g. attaching\nor stripping off a substring)." (cons (regexp :tag "From regexp") (string :tag "To string  ")) vhdl-testbench-include-header vhdl-testbench-declarations "  -- clock\n  signal Clk : std_logic := '1';\n" "String or file to be inserted in the testbench declarative part.\nIf the string specifies an existing file name, the contents of the file is\ninserted, otherwise the string itself is inserted in the testbench\narchitecture before the BEGIN keyword.\nType `C-j' for newlines." vhdl-testbench-statements "  -- clock generation\n  Clk <= not Clk after 10 ns;\n\n  -- waveform generation\n  WaveGen_Proc: process\n  begin\n    -- insert signal assignments here\n\n    wait until Clk = '1';\n  end process WaveGen_Proc;\n" "String or file to be inserted in the testbench statement part.\nIf the string specifies an existing file name, the contents of the file is\ninserted, otherwise the string itself is inserted in the testbench\narchitecture before the END keyword.\nType `C-j' for newlines." vhdl-testbench-initialize-signals "Non-nil means initialize signals with `0' when declared in testbench." vhdl-testbench-include-library "Non-nil means a library/use clause for std_logic_1164 is included." vhdl-testbench-include-configuration "Non-nil means a testbench configuration is attached at the end." vhdl-testbench-create-files 'single "Specifies whether new files should be created for the testbench.\ntestbench entity and architecture are inserted:\n  None          : in current buffer\n  Single file   : in new single file\n  Separate files: in two separate files\nThe file names are obtained from variables `vhdl-testbench-entity-file-name'\nand `vhdl-testbench-architecture-file-name'." (choice (const :tag "None" none) (const :tag "Single file" single) (const :tag "Separate files" separate)) vhdl-testbench-entity-file-name "Specifies how the testbench entity file name is obtained.\nThe entity file name can be obtained by modifying the testbench entity name\n(e.g. attaching or stripping off a substring).  The file extension is\nautomatically taken from the file name of the current buffer.  Testbench\nfiles can be created in a different directory by prepending a relative or\nabsolute path to the file name." (cons (regexp :tag "From regexp") (string :tag "To string  ")) vhdl-testbench-architecture-file-name "Specifies how the testbench architecture file name is obtained.\nThe architecture file name can be obtained by modifying the testbench entity\nand/or architecture name (e.g. attaching or stripping off a substring).  The\nstring that is matched against the regexp is the concatenation of the entity\nand the architecture name separated by a space.  This gives access to both\nnames (see default setting as example).  Testbench files can be created in\na different directory by prepending a relative or absolute path to the file\nname." (cons (regexp :tag "From regexp") (string :tag "To string  ")) vhdl-comment "Customizations for comments." vhdl-self-insert-comments "Non-nil means various templates automatically insert help comments." vhdl-prompt-for-comments "Non-nil means various templates prompt for user definable comments." vhdl-inline-comment-column 40 "Column to indent and align inline comments to.\nOverrides local option `comment-column'.\n\nNOTE: Activate the new setting in a VHDL buffer by using the menu entry\n      \"Activate Options\"." vhdl-end-comment-column 79 "End of comment column.\nComments that exceed this column number are wrapped.\n\nNOTE: Activate the new setting in a VHDL buffer by using the menu entry\n      \"Activate Options\"." vhdl-align "Customizations for alignment." vhdl-auto-align "Non-nil means align some templates automatically after generation." vhdl-align-groups "Non-nil means align groups of code lines separately.\nA group of code lines is a region of consecutive lines between two lines that\nmatch the regexp in option `vhdl-align-group-separate'." vhdl-align-group-separate "^\\s-*$" "Regexp for matching a line that separates groups of lines for alignment.\nExamples:\n  \"^\\s-*$\":          matches an empty line\n  \"^\\s-*\\(--.*\\)?$\": matches an empty line or a comment-only line" regexp vhdl-align-same-indent "Non-nil means align blocks with same indent separately.\nWhen a region or the entire buffer is aligned, the code is divided into\nblocks of same indent which are aligned separately (except for argument/port\nlists).  This gives nicer alignment in most cases.\nOption `vhdl-align-groups' still applies within these blocks." vhdl-highlight "Customizations for highlighting." vhdl-highlight-keywords "Non-nil means highlight VHDL keywords and other standardized words.\nThe following faces are used:\n  `font-lock-keyword-face'       : keywords\n  `font-lock-type-face'          : standardized types\n  `vhdl-font-lock-attribute-face': standardized attributes\n  `vhdl-font-lock-enumvalue-face': standardized enumeration values\n  `vhdl-font-lock-function-face' : standardized function and package names\n\nNOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu\n      entry \"Fontify Buffer\")." #[(variable value) "\302	\303#\207" [variable value vhdl-custom-set vhdl-font-lock-init] 4] vhdl-highlight-names "Non-nil means highlight declaration names and construct labels.\nThe following faces are used:\n  `font-lock-function-name-face' : names in declarations of units,\n     subprograms, components, as well as labels of VHDL constructs\n  `font-lock-type-face'          : names in type/nature declarations\n  `vhdl-font-lock-attribute-face': names in attribute declarations\n  `font-lock-variable-name-face' : names in declarations of signals,\n     variables, constants, subprogram parameters, generics, and ports\n\nNOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu\n      entry \"Fontify Buffer\")." #[(variable value) "\302	\303#\207" [variable value vhdl-custom-set vhdl-font-lock-init] 4] vhdl-highlight-special-words "Non-nil means highlight words with special syntax.\nThe words with syntax and color specified in option `vhdl-special-syntax-alist'\nare highlighted accordingly.\nCan be used for visual support of naming conventions.\n\nNOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu\n      entry \"Fontify Buffer\")." #[(variable value) "\302	\303#\207" [variable value vhdl-custom-set vhdl-font-lock-init] 4] vhdl-highlight-forbidden-words "Non-nil means highlight forbidden words.\nThe reserved words specified in option `vhdl-forbidden-words' or having the\nsyntax specified in option `vhdl-forbidden-syntax' are highlighted in a\nwarning color (face `vhdl-font-lock-reserved-words-face') to indicate not to\nuse them.\n\nNOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu\n      entry \"Fontify Buffer\")." #[(variable value) "\302	\303\304$\207" [variable value vhdl-custom-set vhdl-words-init vhdl-font-lock-init] 5] vhdl-highlight-verilog-keywords "Non-nil means highlight Verilog keywords as reserved words.\nVerilog keywords are highlighted in a warning color (face\n`vhdl-font-lock-reserved-words-face') to indicate not to use them.\n\nNOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu\n      entry \"Fontify Buffer\")." #[(variable value) "\302	\303\304$\207" [variable value vhdl-custom-set vhdl-words-init vhdl-font-lock-init] 5] vhdl-highlight-translate-off "Non-nil means background-highlight code excluded from translation.\nThat is, all code between \"-- pragma translate_off\" and\n\"-- pragma translate_on\" is highlighted using a different background color\n(face `vhdl-font-lock-translate-off-face').\nNote: this might slow down on-the-fly fontification (and thus editing).\n\nNOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu\n      entry \"Fontify Buffer\")." #[(variable value) "\302	\303#\207" [variable value vhdl-custom-set vhdl-font-lock-init] 4] vhdl-highlight-case-sensitive "Non-nil means consider case for highlighting.\nPossible trade-off:\n  non-nil  also upper-case VHDL words are highlighted, but case of words with\n           special syntax is not considered\n  nil      only lower-case VHDL words are highlighted, but case of words with\n           special syntax is considered\nOverrides local option `font-lock-keywords-case-fold-search'.\n\nNOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu\n      entry \"Fontify Buffer\")." vhdl-special-syntax-alist '(("generic/constant" "\\<\\w+_[cg]\\>" "Gold3" "BurlyWood1" nil) ("type" "\\<\\w+_t\\>" "ForestGreen" "PaleGreen" nil) ("variable" "\\<\\w+_v\\>" "Grey50" "Grey80" nil)) "List of special syntax to be highlighted.\nIf option `vhdl-highlight-special-words' is non-nil, words with the specified\nsyntax (as regular expression) are highlighted in the corresponding color.\n\n  Name         : string of words and spaces\n  Regexp       : regular expression describing word syntax\n                 (e.g. \"\\\\=<\\w+_c\\\\=>\" matches word with suffix \"_c\")\n                 expression must start with \"\\\\=<\" and end with \"\\\\=>\"\n                 if only whole words should be matched (no substrings)\n  Color (light): foreground color for light background\n                 (matching color examples: Gold3, Grey50, LimeGreen, Tomato,\n                 LightSeaGreen, DodgerBlue, Gold, PaleVioletRed)\n  Color (dark) : foreground color for dark background\n                 (matching color examples: BurlyWood1, Grey80, Green, Coral,\n                 AquaMarine2, LightSkyBlue1, Yellow, PaleVioletRed1)\n  In comments  : If non-nil, words are also highlighted inside comments\n\nCan be used for visual support of naming conventions, such as highlighting\ndifferent kinds of signals (e.g. \"Clk50\", \"Rst_n\") or objects (e.g.\n\"Signal_s\", \"Variable_v\", \"Constant_c\") by distinguishing them using\ncommon substrings or name suffices.\nFor each entry, a new face is generated with the specified colors and name\n\"vhdl-font-lock-\" + name + \"-face\".\n\nNOTE: Activate a changed regexp in a VHDL buffer by re-fontifying it (menu\n      entry \"Fontify Buffer\").  All other changes require restarting Emacs." (repeat (list :tag "Face" :indent 2 (string :tag "Name         ") (regexp :tag "Regexp       " "\\w+_") (string :tag "Color (light)") (string :tag "Color (dark) ") (boolean :tag "In comments  "))) #[(variable value) "\302	\303#\207" [variable value vhdl-custom-set vhdl-font-lock-init] 4] vhdl-forbidden-words 'nil "List of forbidden words to be highlighted.\nIf option `vhdl-highlight-forbidden-words' is non-nil, these reserved\nwords are highlighted in a warning color to indicate not to use them.\n\nNOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu\n      entry \"Fontify Buffer\")." (repeat (string :format "%v")) #[(variable value) "\302	\303\304$\207" [variable value vhdl-custom-set vhdl-words-init vhdl-font-lock-init] 5] vhdl-forbidden-syntax "Syntax of forbidden words to be highlighted.\nIf option `vhdl-highlight-forbidden-words' is non-nil, words with this\nsyntax are highlighted in a warning color to indicate not to use them.\nCan be used to highlight too long identifiers (e.g. \"\\w\\w\\w\\w\\w\\w\\w\\w\\w\\w+\"\nhighlights identifiers with 10 or more characters).\n\nNOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu\n      entry \"Fontify Buffer\")." #[(variable value) "\302	\303\304$\207" [variable value vhdl-custom-set vhdl-words-init vhdl-font-lock-init] 5] vhdl-directive-keywords '("pragma" "synopsys") "List of compiler directive keywords recognized for highlighting.\n\nNOTE: Activate the new setting in a VHDL buffer by re-fontifying it (menu\n      entry \"Fontify Buffer\")." (repeat (string :format "%v")) #[(variable value) "\302	\303\304$\207" [variable value vhdl-custom-set vhdl-words-init vhdl-font-lock-init] 5] vhdl-speedbar "Customizations for speedbar." vhdl-speedbar-auto-open "Non-nil means automatically open speedbar at startup.\nAlternatively, the speedbar can be opened from the VHDL menu." vhdl-speedbar-display-mode 'files "Specifies the default displaying mode when opening speedbar.\nAlternatively, the displaying mode can be selected from the speedbar menu or\nby typing `f' (files), `h' (directory hierarchy) or `H' (project hierarchy)." (choice (const :tag "Files" files) (const :tag "Directory hierarchy" directory) (const :tag "Project hierarchy" project)) vhdl-speedbar-scan-limit '(10000000 (1000000 50)) "Limits scanning of large files and netlists.\nDesign units: maximum file size to scan for design units\nHierarchy (instances of subcomponents):\n  File size: maximum file size to scan for instances (in bytes)\n  Instances per arch: maximum number of instances to scan per architecture\n\n\"None\" always means that there is no limit.\nIn case of files not or incompletely scanned, a warning message and the file\nnames are printed out.\nBackground: scanning for instances is considerably slower than scanning for\ndesign units, especially when there are many instances.  These limits should\nprevent the scanning of large netlists." (list (choice :tag "Design units" :format "%t        : %[Value Menu%] %v" (const :tag "None" nil) (integer :tag "File size")) (list :tag "Hierarchy" :indent 2 (choice :tag "File size" :format "%t         : %[Value Menu%] %v" (const :tag "None" nil) (integer :tag "Size     ")) (choice :tag "Instances per arch" (const :tag "None" nil) (integer :tag "Number   ")))) vhdl-speedbar-jump-to-unit "Non-nil means jump to the design unit code when opened in a buffer.\nThe buffer cursor position is left unchanged otherwise." vhdl-speedbar-update-on-saving "Automatically update design hierarchy when buffer is saved." vhdl-speedbar-save-cache '(hierarchy display) "Automatically save modified hierarchy caches when exiting Emacs.\n  Hierarchy: design hierarchy information\n  Display:   displaying information (which design units to expand)" (set (const :tag "Hierarchy" hierarchy) (const :tag "Display" display)) vhdl-speedbar-cache-file-name ".emacs-vhdl-cache-\\1-\\2" "Name of file for saving hierarchy cache.\n\"\\1\" is replaced by the project name if a project is specified,\n\"directory\" otherwise.  \"\\2\" is replaced by the user name (allows for\ndifferent users to have cache files in the same directory). Can also have\nan absolute path (i.e. all caches can be stored in one global directory)." vhdl-menu "Customizations for menus." vhdl-index-menu "Non-nil means add an index menu for a source file when loading.\nAlternatively, the speedbar can be used.  Note that the index menu scans a file\nwhen it is opened, while speedbar only scans the file upon request." vhdl-source-file-menu "Non-nil means add a menu of all source files in current directory.\nAlternatively, the speedbar can be used." vhdl-hideshow-menu "Non-nil means add hideshow menu and functionality at startup.\nHideshow can also be enabled from the VHDL Mode menu.\nHideshow allows hiding code of various VHDL constructs.\n\nNOTE: Activate the new setting in a VHDL buffer by using the menu entry\n      \"Activate Options\"." vhdl-hide-all-init "Non-nil means hide all design units initially after a file is loaded." vhdl-print "Customizations for printing." vhdl-print-two-column "Non-nil means print code in two columns and landscape format.\nAdjusts settings in a way that PostScript printing (\"File\" menu, `ps-print')\nprints VHDL files in a nice two-column landscape style.\n\nNOTE: Activate the new setting by restarting Emacs.\n      Overrides `ps-print' settings locally." vhdl-print-customize-faces "Non-nil means use an optimized set of faces for PostScript printing.\n\nNOTE: Activate the new setting by restarting Emacs.\n      Overrides `ps-print' settings locally." vhdl-misc "Miscellaneous customizations." vhdl-intelligent-tab "Non-nil means `TAB' does indentation, word completion and tab insertion.\nThat is, if preceding character is part of a word then complete word,\nelse if not at beginning of line then insert tab,\nelse if last command was a `TAB' or `RET' then dedent one step,\nelse indent current line (i.e. `TAB' is bound to `vhdl-electric-tab').\nIf nil, TAB always indents current line (i.e. `TAB' is bound to\n`indent-according-to-mode').\n\nNOTE: Activate the new setting in a VHDL buffer by using the menu entry\n      \"Activate Options\"." vhdl-indent-syntax-based "Non-nil means indent lines of code based on their syntactic context.\nOtherwise, a line is indented like the previous nonblank line.  This can be\nuseful in large files where syntax-based indentation gets very slow." vhdl-indent-comment-like-next-code-line "*Non-nil means comment lines are indented like the following code line.\nOtherwise, comment lines are indented like the preceding code line.\nIndenting comment lines like the following code line gives nicer indentation\nwhen comments precede the code that they refer to." vhdl-word-completion-case-sensitive "Non-nil means word completion using `TAB' is case sensitive.\nThat is, `TAB' completes words that start with the same letters and case.\nOtherwise, case is ignored." vhdl-word-completion-in-minibuffer "Non-nil enables word completion in minibuffer (for template prompts).\n\nNOTE: Activate the new setting by restarting Emacs." vhdl-underscore-is-part-of-word "Non-nil means consider the underscore character `_' as part of word.\nAn identifier containing underscores is then treated as a single word in\nselect and move operations.  All parts of an identifier separated by underscore\nare treated as single words otherwise.\n\nNOTE: Activate the new setting in a VHDL buffer by using the menu entry\n      \"Activate Options\"." #[(variable value) "\302	\303#\207" [variable value vhdl-custom-set vhdl-mode-syntax-table-init] 4] vhdl-related "Related general customizations." custom-add-to-group hideshow custom-group paren-showing ps-print speedbar comment-style custom-variable line-number-mode transient-mark-mode user-full-name mail-host-address user-mail-address] 30)
#@71 If non-nil, use absolute instead of relative path for compiled files.
(defvar vhdl-compile-absolute-path nil (#$ . 68465))
#@43 Character to use in comment display line.
(defvar vhdl-comment-display-line-char 45 (#$ . 68594))
#@73 Specifies the maximum size of a menu before splitting it into submenus.
(defvar vhdl-menu-max-size 20 (#$ . 68698))
#@203 Interval used to update progress status during long operations.
If a number, percentage complete gets updated after each interval of
that many seconds.  To inhibit all messages, set this option to nil.
(defvar vhdl-progress-interval 1 (#$ . 68821))
#@55 If non-nil, inhibits start up compatibility warnings.
(defvar vhdl-inhibit-startup-warnings-p nil (#$ . 69076))
#@257 If non-nil, all syntactic symbols must be found in `vhdl-offsets-alist'.
If the syntactic symbol for a particular line does not match a symbol
in the offsets alist, an error is generated, otherwise no error is
reported and the syntactic symbol is ignored.
(defvar vhdl-strict-syntax-p nil (#$ . 69195))
#@65 If non-nil, syntactic info is echoed when the line is indented.
(defvar vhdl-echo-syntactic-information-p nil (#$ . 69504))
#@143 Default settings for offsets of syntactic elements.
Do not change this constant!  See the variable `vhdl-offsets-alist' for
more information.
(defconst vhdl-offsets-alist-default '((string . -1000) (cpp-macro . -1000) (block-open . 0) (block-close . 0) (statement . 0) (statement-cont . vhdl-lineup-statement-cont) (statement-block-intro . +) (statement-case-intro . +) (case-alternative . +) (comment . vhdl-lineup-comment) (arglist-intro . +) (arglist-cont . 0) (arglist-cont-nonempty . vhdl-lineup-arglist) (arglist-close . vhdl-lineup-arglist) (entity . 0) (configuration . 0) (package . 0) (architecture . 0) (package-body . 0)) (#$ . 69635))
#@3152 Association list of syntactic element symbols and indentation offsets.
As described below, each cons cell in this list has the form:

    (SYNTACTIC-SYMBOL . OFFSET)

When a line is indented, `vhdl-mode' first determines the syntactic
context of the line by generating a list of symbols called syntactic
elements.  This list can contain more than one syntactic element and
the global variable `vhdl-syntactic-context' contains the context list
for the line being indented.  Each element in this list is actually a
cons cell of the syntactic symbol and a buffer position.  This buffer
position is call the relative indent point for the line.  Some
syntactic symbols may not have a relative indent point associated with
them.

After the syntactic context list for a line is generated, `vhdl-mode'
calculates the absolute indentation for the line by looking at each
syntactic element in the list.  First, it compares the syntactic
element against the SYNTACTIC-SYMBOL's in `vhdl-offsets-alist'.  When it
finds a match, it adds the OFFSET to the column of the relative indent
point.  The sum of this calculation for each element in the syntactic
list is the absolute offset for line being indented.

If the syntactic element does not match any in the `vhdl-offsets-alist',
an error is generated if `vhdl-strict-syntax-p' is non-nil, otherwise
the element is ignored.

Actually, OFFSET can be an integer, a function, a variable, or one of
the following symbols: `+', `-', `++', or `--'.  These latter
designate positive or negative multiples of `vhdl-basic-offset',
respectively: *1, *-1, *2, and *-2.  If OFFSET is a function, it is
called with a single argument containing the cons of the syntactic
element symbol and the relative indent point.  The function should
return an integer offset.

Here is the current list of valid syntactic element symbols:

 string                 -- inside multi-line string
 block-open             -- statement block open
 block-close            -- statement block close
 statement              -- a VHDL statement
 statement-cont         -- a continuation of a VHDL statement
 statement-block-intro  -- the first line in a new statement block
 statement-case-intro   -- the first line in a case alternative block
 case-alternative       -- a case statement alternative clause
 comment                -- a line containing only a comment
 arglist-intro          -- the first line in an argument list
 arglist-cont           -- subsequent argument list lines when no
                           arguments follow on the same line as
                           the arglist opening paren
 arglist-cont-nonempty  -- subsequent argument list lines when at
                           least one argument follows on the same
                           line as the arglist opening paren
 arglist-close          -- the solo close paren of an argument list
 entity                 -- inside an entity declaration
 configuration          -- inside a configuration declaration
 package                -- inside a package declaration
 architecture           -- inside an architecture body
 package-body           -- inside a package body
(defvar vhdl-offsets-alist (copy-alist vhdl-offsets-alist-default) (#$ . 70291))
#@412 Extra offset for line which contains only the start of a comment.
Can contain an integer or a cons cell of the form:

 (NON-ANCHORED-OFFSET . ANCHORED-OFFSET)

Where NON-ANCHORED-OFFSET is the amount of offset given to
non-column-zero anchored comment-only lines, and ANCHORED-OFFSET is
the amount of offset to give column-zero anchored comment-only lines.
Just an integer as value is equivalent to (<val> . 0)
(defvar vhdl-comment-only-line-offset 0 (#$ . 73530))
#@116 Hook for user defined special indentation adjustments.
This hook gets called after a line is indented by the mode.
(defvar vhdl-special-indent-hook nil (#$ . 74002))
#@683 Styles of Indentation.
Elements of this alist are of the form:

  (STYLE-STRING (VARIABLE . VALUE) [(VARIABLE . VALUE) ...])

where STYLE-STRING is a short descriptive string used to select a
style, VARIABLE is any `vhdl-mode' variable, and VALUE is the intended
value for that variable when using the selected style.

There is one special case when VARIABLE is `vhdl-offsets-alist'.  In this
case, the VALUE is a list containing elements of the form:

  (SYNTACTIC-SYMBOL . VALUE)

as described in `vhdl-offsets-alist'.  These are passed directly to
`vhdl-set-offset' so there is no need to set every syntactic symbol in
your style, only those that are different from the default.
(defvar vhdl-style-alist '(("IEEE" (vhdl-basic-offset . 4) (vhdl-offsets-alist))) (#$ . 74175))
(byte-code "\303\304\"\204\305\304\306\307	\"B\211B*\303\207" [vhdl-style-alist varlist default assoc "Default" (vhdl-inhibit-startup-warnings-p vhdl-strict-syntax-p vhdl-echo-syntactic-information-p vhdl-basic-offset vhdl-offsets-alist vhdl-comment-only-line-offset) mapcar #[(var) "\211JB\207" [var] 2]] 5)
#@29 Hook called by `vhdl-mode'.
(defvar vhdl-mode-hook nil (#$ . 75276))
(byte-code "\300\301!\210\300\302!\210\300\303!\210\300\304!\207" [require assoc compile easymenu hippie-exp] 2)
#@108 Do whatever is necessary to keep the region active in XEmacs.
Ignore byte-compiler warnings you might see.
(defalias 'vhdl-keep-region-active #[nil "\300\207" [nil] 1 (#$ . 75465)])
(byte-code "\300\301!\204\302\301\303\"\210\300\304!\204\302\304\305\"\210\300\306!\204!\302\306\307\"\210\300\310!\204,\302\310\311\"\210\300\312!\2047\302\312\313\"\210\300\314!\204B\302\314\315\"\210\300\207" [fboundp wildcard-to-regexp defalias #[(wildcard) "\305\306\"\307	OG	\203<	W\203<	H\n\f\310=\203&\311\2023\f\312=\2030\313\2023\314\f!P	T)\202\315\n\316Q+\207" [wildcard i result len ch string-match "[*?]" 0 42 "[^]*" 63 "[^]" char-to-string "\\`" "\\'"] 3 "Simplified version of `wildcard-to-regexp' from Emacs's `files.el'."] regexp-opt #[(strings &optional paren) "\203\304\202	\305\203\306\202\305\211\307\310\311#	Q*\207" [paren close open strings "\\(" "" "\\)" mapconcat regexp-quote "\\|"] 6] match-string-no-properties match-string subst-char-in-string #[(fromchar tochar string &optional inplace) "G	\203\n\202
\306!\307V\203(S\nH\f=\203\n
I\210\202\n*\207" [string inplace newstr i fromchar tochar copy-sequence 0] 3] file-expand-wildcards #[(pattern &optional full) "\306!\307!\211\203\310\311\n\"\203\312\313\314\315\n!!\"\202 \nC\316\203g@\2035\317\315@!!\203`\320\316\312\321\322@\206@\323
\324	!#\"\"@\203Z
\204Z\312\325\"\202\\\f\244)A\211\204'\f,\207" [pattern nondir dirpart dirs contents full file-name-nondirectory file-name-directory string-match "[[*?]" mapcar file-name-as-directory file-expand-wildcards directory-file-name nil file-directory-p delq #[(name) "\301\302\303!\"?\205\207" [name string-match "\\`\\.\\.?\\'" file-name-nondirectory] 4] directory-files "." wildcard-to-regexp #[(name) "@	P\207" [dirs name] 2] this-dir-contents] 10 "Taken from Emacs's `files.el'."] member-ignore-case member] 3)
#@44 Warnings to tell the user during start up.
(defvar vhdl-warnings nil (#$ . 77393))
#@37 Wait until idle, then run FUNCTION.
(defalias 'vhdl-run-when-idle #[(secs repeat function) "\303\304!\203\304\305	\n\306%\207\307	\n#\310\311I\207" [function secs repeat fboundp start-itimer "vhdl-mode" t run-with-idle-timer 0 nil] 6 (#$ . 77482)])
#@58 Wait until idle, then print out warning STRING and beep.
(defalias 'vhdl-warning-when-idle #[(&rest args) "\203\f\303\304\305	\"\306\"\207\n\204\307\310\311\312#\210\304\305	\"\nB\211\207" [noninteractive args vhdl-warnings vhdl-warning apply format t vhdl-run-when-idle 0.1 nil vhdl-print-warnings] 4 (#$ . 77741)])
#@36 Print out warning STRING and beep.
(defalias 'vhdl-warning #[(string &optional nobeep) "\303\304\"\210	\206\n\n?\205\305 \207" [string nobeep noninteractive message "WARNING:  %s" beep] 3 (#$ . 78069)])
#@49 Print out messages in variable `vhdl-warnings'.
(defalias 'vhdl-print-warnings #[nil "G\237\211\203\302\303@\"\210A\211\204\n\304 \210	\305V\205#\302\306!)\207" [vhdl-warnings no-warnings message "WARNING:  %s" beep 1 "WARNING:  See warnings in message buffer (type `C-c M-m')."] 4 (#$ . 78282)])
(byte-code ";\204\306\307\310!\210	<\204\311\307\312!\210\n@G\313U\203>\n\314\211\2035\315\f@\316\"B\fA\211\204&\237*\317\302\n\"\210
@G\313U\203f
\314\211\203]\315\f@\320\"B\fA\211\204N\237*\317\305
\"\210
@G\321U\203\245
\314\211+\211\203\235\f@\211+@+A@\322\323+8\314\324\325\326\327\313+8\257\nB\fA\211\204y\237+\307\330!\210
@G\331U\203\321
\211,\203\313\313,@\233\322\321,@\233B\241\210,A\211,\204\264)\317\305
\"\210!@G\332U\203(
!\314\211+\211\203
\f@\211+@+A@\322\333\313+8\322\232?\205
\313+8\321+8\326\327+@\227\334+8\335+8\314\257\fB\fA\211\204\346\237!+\307\336!\210!@G\337U\203W
!\211,\203P
\321,@\233\340\334,@\233B\241\210,A\211,\2049
)\317\341!\"\210!@G\342U\203\206
!\211,\203
\313,@\233\322\321,@\233B\241\210,A\211,\204h
)\317\341!\"\210\343!@8G\313U\203\263
!\211,\203\254
\343,@8AA\344\241\210,A\211,\204\231
)\317\341!\"\210%\322\232\203\303
\314%\317\345%\"\210&;\203\324
&C&\317\346&\"\210\347\350!\204\341
\351\323!\210\202\352
\350\352N\204\352
\323(\314\207" [vhdl-compiler vhdl-standard vhdl-model-alist new-alist old-alist vhdl-project-alist "ModelSim" vhdl-warning-when-idle "Option `vhdl-compiler' has changed format; customize again" (87 nil) "Option `vhdl-standard' has changed format; customize again" 3 nil append (#1="") customize-save-variable (#1#) 4 #1# 2 "./" "work" "work/" "Makefile" "Option `vhdl-project-alist' changed format; please re-customize" 10 7 "make -f \\1" 5 6 "Option `vhdl-compiler-alist' changed; please reset and re-customize" 12 "mkdir \\1" vhdl-compiler-alist 13 11 (0) vhdl-project vhdl-project-file-name boundp speedbar-indentation-width (lambda (#2=#:def-tmp-var) (defvar speedbar-indentation-width #2#)) saved-value elem tmp-alist] 13)
#@50 Check if STANDARD is specified as used standard.
(defalias 'vhdl-standard-p #[(standard) "	@=\206	\211A@)>\207" [standard vhdl-standard x] 3 (#$ . 80400)])
#@84 Return non-nil if a project is displayed, i.e. directories or files are
specified.
(defalias 'vhdl-project-p #[(&optional warning) "\303	\"\203	\207\203\n\203\304\305\"\210\306\207" [vhdl-project vhdl-project-alist warning assoc vhdl-warning-when-idle "Project does not exist: \"%s\"" nil] 3 (#$ . 80567)])
#@42 Resolve environment variables in STRING.
(defalias 'vhdl-resolve-env-variable #[(string) "\301\302\"\203\303\304\"\305\303\306\"!\303\307\"Q\202\207" [string string-match "\\(.*\\)${?\\(\\(\\w\\|_\\)+\\)}?\\(.*\\)" match-string 1 getenv 2 4] 5 (#$ . 80889)])
#@118 Return the default directory of the current project or the directory of the
current buffer if no project is defined.
(defalias 'vhdl-default-directory #[nil "\303 \203\304\305\306	\"A@!!\207\n\207" [vhdl-project-alist vhdl-project default-directory vhdl-project-p expand-file-name vhdl-resolve-env-variable aget] 5 (#$ . 81165)])
#@170 Enable case insensitive search and switch to syntax table that includes '_',
then execute BODY, and finally restore the old environment.  Used for
consistent searching.
(defalias 'vhdl-prepare-search-1 '(macro . #[(&rest body) "\301\302\303\304BBE\207" [body let ((case-fold-search t)) with-syntax-table vhdl-mode-ext-syntax-table] 5 (#$ . 81505)]))
#@201 Enable case insensitive search, switch to syntax table that includes '_',
and remove `intangible' overlays, then execute BODY, and finally restore the
old environment.  Used for consistent searching.
(defalias 'vhdl-prepare-search-2 '(macro . #[(&rest body) "\301\302\303\304\305\306B\307BB\257\207" [body let ((case-fold-search t) (current-syntax-table (syntax-table)) overlay-all-list overlay-intangible-list overlay) (set-syntax-table vhdl-mode-ext-syntax-table) (when (fboundp 'overlay-lists) (setq overlay-all-list (overlay-lists)) (setq overlay-all-list (append (car overlay-all-list) (cdr overlay-all-list))) (while overlay-all-list (setq overlay (car overlay-all-list)) (when (memq 'intangible (overlay-properties overlay)) (setq overlay-intangible-list (cons overlay overlay-intangible-list)) (overlay-put overlay 'intangible nil)) (setq overlay-all-list (cdr overlay-all-list)))) unwind-protect progn ((set-syntax-table current-syntax-table) (when (fboundp 'overlay-lists) (while overlay-intangible-list (overlay-put (car overlay-intangible-list) 'intangible t) (setq overlay-intangible-list (cdr overlay-intangible-list)))))] 7 (#$ . 81863)]))
#@40 Visit file FILE-NAME and execute BODY.
(defalias 'vhdl-visit-file '(macro . #[(file-name issue-error &rest body) "\303\304D\305	B\306\307D\310\311\312\313DD\314BB\315\316\317\320\321\305\322\323DD\324\325D\326BBBB\327\303\n\305\330\331\327\332EF\333\334\335E\336BB\337BBBBDFE\320\340\305	B\327\303\n\341BBDFE\342BBBEF\207" [file-name body issue-error if null progn unless file-directory-p let (source-buffer (current-buffer)) visiting-buffer find-buffer-visiting (file-opened) when or (and visiting-buffer (set-buffer visiting-buffer)) condition-case nil set-buffer create-file-buffer (setq file-opened t) vhdl-insert-file-contents ((modify-syntax-entry 45 ". 12" (syntax-table)) (modify-syntax-entry 10 ">" (syntax-table)) (modify-syntax-entry 13 ">" (syntax-table)) (modify-syntax-entry 95 "w" (syntax-table)) t) error (when file-opened (kill-buffer (current-buffer))) (set-buffer source-buffer) "ERROR:  File cannot be opened: \"%s\"" vhdl-warning format "File cannot be opened: \"%s\"" (t) (nil) info ((progn (when file-opened (kill-buffer (current-buffer))) (set-buffer source-buffer) (error (cadr info))) (vhdl-warning (cadr info))) ((when file-opened (kill-buffer (current-buffer))) (set-buffer source-buffer))] 22 (#$ . 83026)]))
#@83 Nicked from `insert-file-contents-literally', but allow coding system
conversion.
(defalias 'vhdl-insert-file-contents #[(filename) "\304\211\211\305\306\"+\207" [jka-compr-compression-info-list after-insert-file-functions format-alist filename nil insert-file-contents t] 3 (#$ . 84277)])
#@13 Sort ALIST.
(defalias 'vhdl-sort-alist #[(alist) "\301\302\"\207" [alist sort #[(a b) "@	@\231\207" [a b] 2]] 3 (#$ . 84577)])
#@46 Recursively get subdirectories of DIRECTORY.
(defalias 'vhdl-get-subdirs #[(directory) "\303!C\304\305\306\307#\211\203'\310	@!\203 \311\n\312	@!\"	A\211\204\n*\207" [directory file-list dir-list file-name-as-directory nil vhdl-directory-files t "\\w.*" file-directory-p append vhdl-get-subdirs] 5 (#$ . 84712)])
#@55 As `aput', but delete key-value pair if VALUE is nil.
(defalias 'vhdl-aput #[(alist-symbol key &optional value) "\203\n\303	\n#\207\304	\n\"\207" [value alist-symbol key aput adelete] 4 (#$ . 85042)])
#@72 Delete by side effect the first occurrence of ELT as a member of LIST.
(defalias 'vhdl-delete #[(elt list) "\304B\211\211A\203\n	\211A@)\232\204	A\211\202\203*	\211\211AA)\241\210)A\207" [list list1 elt x nil] 3 (#$ . 85252)])
#@45 Refresh directory or project with name KEY.
(defalias 'vhdl-speedbar-refresh #[(&optional key) "\304\300!\205C\305!\205C`\306 \204\307 \202B\310!\210\212eb\210\311\312\313Q\314\315#)\203?\316\225b\210\317 \210\320u\210\317 \210\321\322!\210\310	!*\207" [speedbar-frame last-frame pos key boundp frame-live-p selected-frame speedbar-refresh select-frame re-search-forward "^\\([0-9]+:\\s-*<\\)->\\s-+" "$" nil t 1 speedbar-do-function-pointer -2 message "Refreshing speedbar...done"] 4 (#$ . 85500)])
#@48 Get *Messages* buffer to show recent messages.
(defalias 'vhdl-show-messages #[nil "\300\301!\207" [display-buffer "*Messages*"] 2 (#$ . 86018) nil])
#@46 Return whether direct instantiation is used.
(defalias 'vhdl-use-direct-instantiation #[nil "\301=\206\302=\205\303\304!?\207" [vhdl-use-direct-instantiation always standard vhdl-standard-p 87] 2 (#$ . 86174)])
#@23 Return larger marker.
(defalias 'vhdl-max-marker #[(marker1 marker2) "	V\203\207	\207" [marker1 marker2] 2 (#$ . 86397)])
#@36 Goto marker in appropriate buffer.
(defalias 'vhdl-goto-marker #[(marker) "\301!\203\302!q\210b\207" [marker markerp marker-buffer] 2 (#$ . 86529)])
#@86 Split menu LIST into several submenus, if number of
elements > `vhdl-menu-max-size'.
(defalias 'vhdl-menu-split #[(list title) "G	V\203U\306\211\307\310\203A@\fBA\nT\211	U\203\311\312\f#\f\237B
B\310T\306\202\f\203Q\311\312\f#\f\237B
B
\237-\207\207" [list vhdl-menu-max-size i menuno sublist result nil 1 0 format "%s %s" remain title] 6 (#$ . 86689)])
#@28 Keymap for VHDL templates.
(defvar vhdl-template-map nil (#$ . 87085))
#@33 Initialize `vhdl-template-map'.
(defalias 'vhdl-template-map-init #[nil "\301 \302\303\304#\210\302\305\306#\210\302\307\310#\210\302\311\312#\210\302\313\314#\210\302\315\316#\210\302\317\320#\210\302\321\322#\210\302\323\324#\210\302\325\326#\210\302\327\330#\210\302\331\332#\210\302\333\334#\210\302\335\336#\210\302\337\340#\210\302\341\342#\210\302\343\344#\210\302\345\346#\210\302\347\350#\210\302\351\352#\210\302\353\354#\210\302\355\356#\210\302\357\360#\210\302\361\362#\210\302\363\364#\210\302\365\366#\210\302\367\370#\210\302\371\372#\210\302\373\374#\210\302\375\376#\210\302\377\201@#\210\302\201A\201B#\210\302\201C\201D#\210\302\201E\201F#\210\302\201G\201H#\210\302\201I\201J#\210\302\201K\300#\210\302\201L\201M#\210\302\201N\201O#\210\302\201P\201Q#\210\302\201R\201S#\210\302\201T\201U#\210\302\201V\201W#\210\302\201X\201Y#\210\302\201Z\201[#\210\302\201\\\201]#\210\302\201^\201_#\210\302\201`\201a#\210\302\201b\201c#\210\302\201d\201e#\210\302\201f\201g#\210\302\201h\201i#\210\302\201j\201k#\210\302\201l\201m#\210\302\201n\201o#\210\302\201p\201q#\210\302\201r\201s#\210\302\201t\201u#\210\302\201v\201w#\210\302\201x\201y#\210\302\201z\201{#\210\302\201|\201}#\210\302\201~\201#\210\302\201\200\201\201#\210\302\201\202\201\203#\210\302\201\204\201\205#\210\302\201\206\201\207#\210\302\201\210\201\211#\210\302\201\212\201\213#\210\302\201\214\201\215#\210\302\201\216\201\217#\210\302\201\220\201\221#\210\302\201\222\201\223#\210\201\224\201\225!\203\331\302\201\226\201\227#\210\302\201\230\201\231#\210\302\201\232\201\233#\210\302\201\234\201\235#\210\302\201\236\201\237#\210\302\201\240\201\241#\210\302\201\242\201\243#\210\302\201\244\201\245#\210\302\201\246\201\247#\210\302\201\250\201\251#\210\302\201\252\201\253#\210\201\224\201\254!\205\366\302\201\255\201\256#\210\302\201\257\201\260#\207" [vhdl-template-map make-sparse-keymap define-key "al" vhdl-template-alias "ar" vhdl-template-architecture "at" vhdl-template-assert "ad" vhdl-template-attribute-decl "as" vhdl-template-attribute-spec "bl" vhdl-template-block "ca" vhdl-template-case-is "cd" vhdl-template-component-decl "ci" vhdl-template-component-inst "cs" vhdl-template-conditional-signal-asst "Cb" vhdl-template-block-configuration "Cc" vhdl-template-component-conf "Cd" vhdl-template-configuration-decl "Cs" vhdl-template-configuration-spec "co" vhdl-template-constant "di" vhdl-template-disconnect "el" vhdl-template-else "ei" vhdl-template-elsif "en" vhdl-template-entity "ex" vhdl-template-exit "fi" vhdl-template-file "fg" vhdl-template-for-generate "fl" vhdl-template-for-loop "" vhdl-template-footer "fb" vhdl-template-function-body "fd" vhdl-template-function-decl "ge" vhdl-template-generic "gd" vhdl-template-group-decl "gt" vhdl-template-group-template "" vhdl-template-header "ig" vhdl-template-if-generate "it" vhdl-template-if-then "li" vhdl-template-library "lo" vhdl-template-bare-loop "
" vhdl-template-modify "" vhdl-template-insert-date "ma" "ne" vhdl-template-next "ot" vhdl-template-others "Pd" vhdl-template-package-decl "Pb" vhdl-template-package-body "(" vhdl-template-paired-parens "po" vhdl-template-port "pb" vhdl-template-procedure-body "pd" vhdl-template-procedure-decl "pc" vhdl-template-process-comb "ps" vhdl-template-process-seq "rp" vhdl-template-report "rt" vhdl-template-return "ss" vhdl-template-selected-signal-asst "si" vhdl-template-signal "su" vhdl-template-subtype "ty" vhdl-template-type "us" vhdl-template-use "va" vhdl-template-variable "wa" vhdl-template-wait "wl" vhdl-template-while-loop "wi" vhdl-template-with "wc" vhdl-template-clocked-wait "b" vhdl-template-package-numeric-bit "n" vhdl-template-package-numeric-std "s" vhdl-template-package-std-logic-1164 "A" vhdl-template-package-std-logic-arith "M" vhdl-template-package-std-logic-misc "S" vhdl-template-package-std-logic-signed "T" vhdl-template-package-std-logic-textio "U" vhdl-template-package-std-logic-unsigned "t" vhdl-template-package-textio "n" vhdl-template-directive-translate-on "f" vhdl-template-directive-translate-off "N" vhdl-template-directive-synthesis-on "F" vhdl-template-directive-synthesis-off "" vhdl-template-search-prompt vhdl-standard-p ams "br" vhdl-template-break "cu" vhdl-template-case-use "iu" vhdl-template-if-use "lm" vhdl-template-limit "na" vhdl-template-nature "pa" vhdl-template-procedural "qf" vhdl-template-quantity-free "qb" vhdl-template-quantity-branch "qs" vhdl-template-quantity-source "sn" vhdl-template-subnature "te" vhdl-template-terminal math "c" vhdl-template-package-math-complex "r" vhdl-template-package-math-real] 4 (#$ . 87162)])
(vhdl-template-map-init)
#@177 Generate a Lisp function name.
PREFIX, STRING and optional POSTFIX are concatenated by '-' and spaces in
STRING are replaced by `-' and substrings are converted to lower case.
(defalias 'vhdl-function-name #[(prefix string &optional postfix) "\304\305\n\"\203	\306\n\307\310\225O\227Q\n\311\224\312O\202\203%	\306Q\313	!)\207" [prefix name string postfix string-match "\\(\\w+\\)\\s-*\\(.*\\)" "-" 0 1 2 nil intern] 5 (#$ . 92018)])
#@25 Keymap for VHDL models.
(defvar vhdl-model-map nil (#$ . 92469))
#@30 Initialize `vhdl-model-map'.
(defalias 'vhdl-model-map-init #[nil "\304 	\305\211\205\"@\306\307\n8\310\311\n@\"#\210A\211\204\305*\207" [vhdl-model-map vhdl-model-alist model model-alist make-sparse-keymap nil define-key 2 vhdl-function-name "vhdl-model"] 7 (#$ . 92540)])
(vhdl-model-map-init)
#@23 Keymap for VHDL Mode.
(defvar vhdl-mode-map nil (#$ . 92853))
#@29 Initialize `vhdl-mode-map'.
(defalias 'vhdl-mode-map-init #[nil "\304 \305\306	#\210\305\307\n#\210\305\310\311#\210\305\312\313#\210\305\314\315#\210\305\316\317#\210\305\320\321#\210\305\322\323#\210\305\324\325#\210\305\326\327#\210\305\330\331#\210\305\332\333#\210\305\334\335#\210\336\337!\204c\305\340\341#\210\305\342\343#\210\305\344\345#\210\305\346\347#\210\305\350\351#\210\305\352\353#\210\305\354\355#\210\305\356\357#\210\305\360\361#\210\305\362\363#\210\305\364\365#\210\305\366\367#\210\305\370\371#\210\305\372\371#\210\305\373\374#\210\305\375\376#\210\305\377\201@#\210\305\201A\201B#\210\305\201C\201D#\210\305\201E\201F#\210\305\201G\201H#\210\305\201I\201J#\210\305\201K\201L#\210\305\201M\201N#\210\305\201O\201P#\210\305\201Q\201P#\210\305\201R\201S#\210\305\201T\201U#\210\305\201V\201W#\210\305\201X\201Y#\210\305\201Z\201[#\210\305\201\\\201]#\210\305\201^\201_#\210\305\201`\201a#\210\305\201b\201c#\210\305\201d\201e#\210\305\201f\201g#\210\305\201h\201i#\210\305\201j\201k#\210\305\201l\201m#\210\305\201n\201o#\210\305\201p\201q#\210\305\201r\201s#\210\305\201t\201s#\210\305\201u\201v#\210\305\201w\201x#\210\305\201y\201z#\210\305\201{\201|#\210\305\201}\201~#\210\305\201\201\200#\210\305\201\201\201\202#\210\305\201\203\201\204#\210\305\201\205\201\204#\210\305\201\206\201\207#\210\305\201\210\201\211#\210\305\201\212\201\213#\210\305\201\214\201\215#\210\305\201\216\201\217#\210\305\201\220\201\221#\210\305\201\222\201\223#\210\305\201\224\201\225#\210\305\201\226\201\227#\210\305\201\230\201\231#\210\305\201\232\201\233#\210\305\201\234\201\235#\210\305\201\236\201\237#\210\305\201\240\201\241#\210\305\201\242\201\243#\210\305\201\244\201\245#\210\305\201\246\201\247#\210\305\201\250\201\251#\210\305\201\252\201\253#\210\305\201\254\201\255#\210\305\201\256\201\257#\210\305\201\260\201\261#\210\305\201\262\201\263#\210\305\201\264\201\265#\210\305\201\266\201\267#\210\305\201\270\201\271#\210\305\201\272\201\273#\210\305\201\274\201\275#\210\305\201\276\201\277#\210\305\201\300\201\301#\210\305\201\302\201\303#\210\305\201\304\201\305#\210\203u\305\201\306\201\307#\210\305\201\310\201\311#\210\305\201\312\201\313#\210\305\201\314\201\315#\210\305\201\316\201\317#\210\305\201\320\201\321#\210\305\201\322\201\323#\210\305\201\324\201\325#\210\305\201\326\201\327#\210\201\330\201\331!\205\330\305\201\332\201\333#\207" [vhdl-mode-map vhdl-template-map vhdl-model-map vhdl-intelligent-tab make-sparse-keymap define-key "" "
" "\341" vhdl-beginning-of-statement "\345" vhdl-end-of-statement "\206" vhdl-forward-sexp "\202" vhdl-backward-sexp "\225" vhdl-backward-up-list "\201" vhdl-backward-same-indent "\205" vhdl-forward-same-indent "\210" vhdl-mark-defun "\221" vhdl-indent-sexp "\336" vhdl-delete-indentation [backspace] backward-delete-char-untabify boundp delete-key-deletes-forward [delete] delete-char [(meta delete)] kill-word "
" vhdl-electric-mode "
" vhdl-stutter-mode "" vhdl-set-project "" vhdl-duplicate-project "
" vhdl-import-project "" vhdl-export-project "" vhdl-set-compiler "" vhdl-compile "\213" vhdl-make "\353" vhdl-generate-makefile "" vhdl-port-copy "\367" "" vhdl-port-paste-entity "" vhdl-port-paste-component "	" vhdl-port-paste-instance "" vhdl-port-paste-signals "\343" vhdl-port-paste-constants "" vhdl-port-paste-generic-map "" vhdl-port-paste-initializations "" vhdl-port-paste-testbench "" vhdl-port-flatten "" vhdl-port-reverse-direction "" vhdl-subprog-copy "\367" "" vhdl-subprog-paste-declaration "" vhdl-subprog-paste-body "" vhdl-subprog-paste-call "" vhdl-subprog-flatten "
" vhdl-compose-new-component "
" vhdl-compose-place-component "
" vhdl-compose-wire-components "
" vhdl-compose-configuration "
" vhdl-compose-components-package "" vhdl-comment-uncomment-region "-" vhdl-comment-append-inline "\255" vhdl-comment-display-line "	\f" indent-according-to-mode "	" vhdl-indent-group "\234" vhdl-indent-region "	" vhdl-indent-buffer "
" vhdl-align-group "

" "
	" vhdl-align-same-indent "
\f" vhdl-align-list "
" vhdl-align-declarations "
\341" vhdl-align-region "
" vhdl-align-buffer "
" vhdl-align-inline-comment-group "
\343" vhdl-align-inline-comment-region "\f" vhdl-fill-list "" "" vhdl-fill-group "	" vhdl-fill-same-indent "\346" vhdl-fill-region "\f" vhdl-line-kill "\f\367" vhdl-line-copy "\f" vhdl-line-yank "\f	" vhdl-line-expand "\f" vhdl-line-transpose-next "\f" vhdl-line-transpose-previous "\f" vhdl-line-open "\f" goto-line "\f" vhdl-comment-uncomment-line "" vhdl-fix-clause "\343" vhdl-fix-case-region "" vhdl-fix-case-buffer "\367" vhdl-fixup-whitespace-region "" vhdl-fixup-whitespace-buffer "\342" vhdl-beautify-region "" vhdl-beautify-buffer "" vhdl-update-sensitivity-list-process "\363" vhdl-update-sensitivity-list-buffer "	" vhdl-fontify-buffer "	" vhdl-statistics-buffer "\355" vhdl-show-messages "" vhdl-doc-mode "" vhdl-version "\211" insert-tab "	" vhdl-template-insert-construct "	" vhdl-template-insert-package "	" vhdl-template-insert-directive "	
" vhdl-model-insert " " vhdl-electric-space "	" vhdl-electric-tab "
" vhdl-electric-return "-" vhdl-electric-dash "[" vhdl-electric-open-bracket "]" vhdl-electric-close-bracket "'" vhdl-electric-quote ";" vhdl-electric-semicolon "," vhdl-electric-comma "." vhdl-electric-period vhdl-standard-p ams "=" vhdl-electric-equal] 4 (#$ . 92921)])
(vhdl-mode-map-init)
#@42 Keymap for minibuffer used in VHDL Mode.
(defvar vhdl-minibuffer-local-map (byte-code "\303 \304	\"\210\n\203\305\306\307#\210)\207" [map minibuffer-local-map vhdl-word-completion-in-minibuffer make-sparse-keymap set-keymap-parent define-key "	" vhdl-minibuffer-tab] 4) (#$ . 98715))
(mapc #[(sym) "\301\302\303#\210\301\304\303#\207" [sym put delete-selection t pending-delete] 4] '(vhdl-electric-space vhdl-electric-tab vhdl-electric-return vhdl-electric-dash vhdl-electric-open-bracket vhdl-electric-close-bracket vhdl-electric-quote vhdl-electric-semicolon vhdl-electric-comma vhdl-electric-period vhdl-electric-equal))
#@43 Syntax table used in `vhdl-mode' buffers.
(defvar vhdl-mode-syntax-table nil (#$ . 99353))
#@59 Syntax table extended by `_' used in `vhdl-mode' buffers.
(defvar vhdl-mode-ext-syntax-table nil (#$ . 99450))
#@38 Initialize `vhdl-mode-syntax-table'.
(defalias 'vhdl-mode-syntax-table-init #[nil "\303 \304\305\306#\210\304\307\306#\210\304\310\306#\210\304\311\306#\210\304\312\306#\210\304\313\306#\210\304\314\306#\210\304\315\306#\210\304\316\306#\210\304\317\306#\210\304\320\306#\210\304\321\306#\210\304\322\306#\210\304\323\306#\210\304\324\306#\210\304\325\306#\210\304\326\327#\210	\203s\304\330\331#\210\304\332\333#\210\304\334\335#\210\304\336\335#\210\304\337\340#\210\304\341\342#\210\304\343\344#\210\304\345\346#\210\304\347\350#\210\304\351\352#\210\353!\304\330\331\n#\207" [vhdl-mode-syntax-table vhdl-underscore-is-part-of-word vhdl-mode-ext-syntax-table make-syntax-table modify-syntax-entry 35 "." 36 37 38 39 42 43 46 47 58 59 60 61 62 92 124 34 "\"" 95 "w" 45 ". 12" 10 ">" 13 40 "()" 41 ")(" 91 "(]" 93 ")[" 123 "(}" 125 "){" copy-syntax-table] 4 (#$ . 99567)])
(vhdl-mode-syntax-table-init)
#@59 Buffer local variable containing syntactic analysis list.
(defvar vhdl-syntactic-context nil (#$ . 100508))
(make-variable-buffer-local 'vhdl-syntactic-context)
#@45 Abbrev table to use in `vhdl-mode' buffers.
(defvar vhdl-mode-abbrev-table nil (#$ . 100675))
#@38 Initialize `vhdl-mode-abbrev-table'.
(defalias 'vhdl-mode-abbrev-table-init #[nil "\306\307\310\311>\205
\312\313\314\"\311>\205\315\316!\205\312\317\320\"\321>\205U\322\211\322\211\203R
@\323\f8\211\324\232\204K	\324\325\326\f@\327#\330\331\257\nB
A\211\204/*\n*#\"\207" [vhdl-electric-keywords keyword abbrev-list vhdl-model-alist elem --dolist-tail-- define-abbrev-table vhdl-mode-abbrev-table append vhdl mapcar #[(x) "@\301A\302\303\257\207" [x #1="" 0 system] 5] (("--" . vhdl-template-display-comment-hook) ("abs" . vhdl-template-default-hook) ("access" . vhdl-template-default-hook) ("after" . vhdl-template-default-hook) ("alias" . vhdl-template-alias-hook) ("all" . vhdl-template-default-hook) ("and" . vhdl-template-default-hook) ("arch" . vhdl-template-architecture-hook) ("architecture" . vhdl-template-architecture-hook) ("array" . vhdl-template-default-hook) ("assert" . vhdl-template-assert-hook) ("attr" . vhdl-template-attribute-hook) ("attribute" . vhdl-template-attribute-hook) ("begin" . vhdl-template-default-indent-hook) ("block" . vhdl-template-block-hook) ("body" . vhdl-template-default-hook) ("buffer" . vhdl-template-default-hook) ("bus" . vhdl-template-default-hook) ("case" . vhdl-template-case-hook) ("comp" . vhdl-template-component-hook) ("component" . vhdl-template-component-hook) ("cond" . vhdl-template-conditional-signal-asst-hook) ("conditional" . vhdl-template-conditional-signal-asst-hook) ("conf" . vhdl-template-configuration-hook) ("configuration" . vhdl-template-configuration-hook) ("cons" . vhdl-template-constant-hook) ("constant" . vhdl-template-constant-hook) ("disconnect" . vhdl-template-disconnect-hook) ("downto" . vhdl-template-default-hook) ("else" . vhdl-template-else-hook) ("elseif" . vhdl-template-elsif-hook) ("elsif" . vhdl-template-elsif-hook) ("end" . vhdl-template-default-indent-hook) ("entity" . vhdl-template-entity-hook) ("exit" . vhdl-template-exit-hook) ("file" . vhdl-template-file-hook) ("for" . vhdl-template-for-hook) ("func" . vhdl-template-function-hook) ("function" . vhdl-template-function-hook) ("generic" . vhdl-template-generic-hook) ("group" . vhdl-template-group-hook) ("guarded" . vhdl-template-default-hook) ("if" . vhdl-template-if-hook) ("impure" . vhdl-template-default-hook) ("in" . vhdl-template-default-hook) ("inertial" . vhdl-template-default-hook) ("inout" . vhdl-template-default-hook) ("inst" . vhdl-template-instance-hook) ("instance" . vhdl-template-instance-hook) ("is" . vhdl-template-default-hook) ("label" . vhdl-template-default-hook) ("library" . vhdl-template-library-hook) ("linkage" . vhdl-template-default-hook) ("literal" . vhdl-template-default-hook) ("loop" . vhdl-template-bare-loop-hook) ("map" . vhdl-template-map-hook) ("mod" . vhdl-template-default-hook) ("nand" . vhdl-template-default-hook) ("new" . vhdl-template-default-hook) ("next" . vhdl-template-next-hook) ("nor" . vhdl-template-default-hook) ("not" . vhdl-template-default-hook) ("null" . vhdl-template-default-hook) ("of" . vhdl-template-default-hook) ("on" . vhdl-template-default-hook) ("open" . vhdl-template-default-hook) ("or" . vhdl-template-default-hook) ("others" . vhdl-template-others-hook) ("out" . vhdl-template-default-hook) ("pack" . vhdl-template-package-hook) ("package" . vhdl-template-package-hook) ("port" . vhdl-template-port-hook) ("postponed" . vhdl-template-default-hook) ("procedure" . vhdl-template-procedure-hook) ("process" . vhdl-template-process-hook) ("pure" . vhdl-template-default-hook) ("range" . vhdl-template-default-hook) ("record" . vhdl-template-default-hook) ("register" . vhdl-template-default-hook) ("reject" . vhdl-template-default-hook) ("rem" . vhdl-template-default-hook) ("report" . vhdl-template-report-hook) ("return" . vhdl-template-return-hook) ("rol" . vhdl-template-default-hook) ("ror" . vhdl-template-default-hook) ("select" . vhdl-template-selected-signal-asst-hook) ("severity" . vhdl-template-default-hook) ("shared" . vhdl-template-default-hook) ("sig" . vhdl-template-signal-hook) ("signal" . vhdl-template-signal-hook) ("sla" . vhdl-template-default-hook) ("sll" . vhdl-template-default-hook) ("sra" . vhdl-template-default-hook) ("srl" . vhdl-template-default-hook) ("subtype" . vhdl-template-subtype-hook) ("then" . vhdl-template-default-hook) ("to" . vhdl-template-default-hook) ("transport" . vhdl-template-default-hook) ("type" . vhdl-template-type-hook) ("unaffected" . vhdl-template-default-hook) ("units" . vhdl-template-default-hook) ("until" . vhdl-template-default-hook) ("use" . vhdl-template-use-hook) ("var" . vhdl-template-variable-hook) ("variable" . vhdl-template-variable-hook) ("wait" . vhdl-template-wait-hook) ("when" . vhdl-template-when-hook) ("while" . vhdl-template-while-loop-hook) ("with" . vhdl-template-with-hook) ("xnor" . vhdl-template-default-hook) ("xor" . vhdl-template-default-hook)) vhdl-standard-p ams #[(x) "@\301A\302\303\257\207" [x #1# 0 system] 5] (("across" . vhdl-template-default-hook) ("break" . vhdl-template-break-hook) ("limit" . vhdl-template-limit-hook) ("nature" . vhdl-template-nature-hook) ("noise" . vhdl-template-default-hook) ("procedural" . vhdl-template-procedural-hook) ("quantity" . vhdl-template-quantity-hook) ("reference" . vhdl-template-default-hook) ("spectrum" . vhdl-template-default-hook) ("subnature" . vhdl-template-subnature-hook) ("terminal" . vhdl-template-terminal-hook) ("through" . vhdl-template-default-hook) ("tolerance" . vhdl-template-default-hook)) user nil 3 #1# vhdl-function-name "vhdl-model" "hook" 0 system] 12 (#$ . 100775)])
(vhdl-mode-abbrev-table-init)
#@39 List of built-in construct templates.
(defvar vhdl-template-construct-alist nil (#$ . 106391))
#@45 Initialize `vhdl-template-construct-alist'.
(defalias 'vhdl-template-construct-alist-init #[nil "\301\302\303\304!\205	\305\"\211\207" [vhdl-template-construct-alist append (("alias declaration" vhdl-template-alias) ("architecture body" vhdl-template-architecture) ("assertion" vhdl-template-assert) ("attribute declaration" vhdl-template-attribute-decl) ("attribute specification" vhdl-template-attribute-spec) ("block configuration" vhdl-template-block-configuration) ("block statement" vhdl-template-block) ("case statement" vhdl-template-case-is) ("component configuration" vhdl-template-component-conf) ("component declaration" vhdl-template-component-decl) ("component instantiation statement" vhdl-template-component-inst) ("conditional signal assignment" vhdl-template-conditional-signal-asst) ("configuration declaration" vhdl-template-configuration-decl) ("configuration specification" vhdl-template-configuration-spec) ("constant declaration" vhdl-template-constant) ("disconnection specification" vhdl-template-disconnect) ("entity declaration" vhdl-template-entity) ("exit statement" vhdl-template-exit) ("file declaration" vhdl-template-file) ("generate statement" vhdl-template-generate) ("generic clause" vhdl-template-generic) ("group declaration" vhdl-template-group-decl) ("group template declaration" vhdl-template-group-template) ("if statement" vhdl-template-if-then) ("library clause" vhdl-template-library) ("loop statement" vhdl-template-loop) ("next statement" vhdl-template-next) ("package declaration" vhdl-template-package-decl) ("package body" vhdl-template-package-body) ("port clause" vhdl-template-port) ("process statement" vhdl-template-process) ("report statement" vhdl-template-report) ("return statement" vhdl-template-return) ("selected signal assignment" vhdl-template-selected-signal-asst) ("signal declaration" vhdl-template-signal) ("subprogram declaration" vhdl-template-subprogram-decl) ("subprogram body" vhdl-template-subprogram-body) ("subtype declaration" vhdl-template-subtype) ("type declaration" vhdl-template-type) ("use clause" vhdl-template-use) ("variable declaration" vhdl-template-variable) ("wait statement" vhdl-template-wait)) vhdl-standard-p ams (("break statement" vhdl-template-break) ("nature declaration" vhdl-template-nature) ("quantity declaration" vhdl-template-quantity) ("simultaneous case statement" vhdl-template-case-use) ("simultaneous if statement" vhdl-template-if-use) ("simultaneous procedural statement" vhdl-template-procedural) ("step limit specification" vhdl-template-limit) ("subnature declaration" vhdl-template-subnature) ("terminal declaration" vhdl-template-terminal))] 4 (#$ . 106492)])
(vhdl-template-construct-alist-init)
#@37 List of built-in package templates.
(defvar vhdl-template-package-alist nil (#$ . 109214))
#@43 Initialize `vhdl-template-package-alist'.
(defalias 'vhdl-template-package-alist-init #[nil "\301\302\303\304!\205	\305\"\211\207" [vhdl-template-package-alist append (("numeric_bit" vhdl-template-package-numeric-bit) ("numeric_std" vhdl-template-package-numeric-std) ("std_logic_1164" vhdl-template-package-std-logic-1164) ("std_logic_arith" vhdl-template-package-std-logic-arith) ("std_logic_misc" vhdl-template-package-std-logic-misc) ("std_logic_signed" vhdl-template-package-std-logic-signed) ("std_logic_textio" vhdl-template-package-std-logic-textio) ("std_logic_unsigned" vhdl-template-package-std-logic-unsigned) ("textio" vhdl-template-package-textio)) vhdl-standard-p math (("math_complex" vhdl-template-package-math-complex) ("math_real" vhdl-template-package-math-real))] 4 (#$ . 109311)])
(vhdl-template-package-alist-init)
#@39 List of built-in directive templates.
(defvar vhdl-template-directive-alist '(("translate_on" vhdl-template-directive-translate-on) ("translate_off" vhdl-template-directive-translate-off) ("synthesis_on" vhdl-template-directive-synthesis-on) ("synthesis_off" vhdl-template-directive-synthesis-off)) (#$ . 110157))
#@54 Call the customize function with `vhdl' as argument.
(defalias 'vhdl-customize #[nil "\300\301!\207" [customize-browse vhdl] 2 (#$ . 110477) nil])
#@24 Create VHDL Mode menu.
(defalias 'vhdl-create-mode-menu #[nil "\306\307\310\311\211\211\203-\211@@)\312	\313	D\314\315\316\317	\320BB&\nBA\211\204

\2038\321\n\322\"\202:\n\237\323\n\324\"+\325#\326\327\330\331\326\332\333\326\334\335\336\326\307\337@\311\211\211A\203\200A\211@@)\312	\340\341	E\314\315\316\317	\342BB&\nBAA\211A\204\\\n\237\323\n\343\"+\344#\257\f\326\307\345\346\347!\205\226\350\351\307\352\353\346\347!\205\241\354\346\355!\205\250\356\357%C\360%\307\361B\311\211C\211D\203\341D@C\312C@\362\363C@\"\364\365\366\367C8!P$\nBDA\211D\204\274\n\237\323\n\370\"+\371#\372\373\374\326\375\376\377\326\201E\201F\201G\201H\201I\201J\326\201K\201L\201M\201N\326\201O\201P\326\201Q\201R\201S\326\201T\201U\324\201V\307\201W\311\211\211\203j
\211@@)\312	\201X\201Y\201Z	E\313	DE\314\315\316\317	\201[BB&\nBA\211\204<
\n\237\323\n\324\"+\"\201\\BBB\343\201]\307\201^@\311\211\211A\203\267
A\211@@)\312	\201Y\201_	E\314\315\316\317	\201`BB&\nBAA\211A\204\215
\n\237\323\n\343\"+\"\201aBBB\201bBBBB\257#\207" [vhdl-project-alist name menu-list project-alist x vhdl-project-sort "VHDL" append ("Project" ["None" (vhdl-set-project #1="") :style radio :selected (null vhdl-project)] "--") nil vector vhdl-set-project :style radio :selected equal (vhdl-project) sort #[(a b) "\302\234	\302\234\231\207" [a b 0] 3] vhdl-menu-split "Project" ("--" "--" ["Select Project..." vhdl-set-project t] ["Set As Default Project" vhdl-set-default-project t] "--" ["Duplicate Project" vhdl-duplicate-project vhdl-project] ["Import Project..." vhdl-import-project :keys "C-c C-p C-m" :active t] ["Export Project" vhdl-export-project vhdl-project] "--" ["Customize Project..." (customize-option 'vhdl-project-alist) t]) "--" "Compile" ["Compile Buffer" vhdl-compile t] ["Stop Compilation" kill-compilation t] ["Make" vhdl-make t] ["Generate Makefile" vhdl-generate-makefile t] ["Next Error" next-error t] ["Previous Error" previous-error t] ["First Error" first-error t] ("Compiler") setq vhdl-compiler (vhdl-compiler) "Compiler" ("--" "--" ["Select Compiler..." vhdl-set-compiler t] "--" ["Customize Compiler..." (customize-option 'vhdl-compiler-alist) t]) ("Template" ("VHDL Construct 1" ["Alias" vhdl-template-alias t] ["Architecture" vhdl-template-architecture t] ["Assert" vhdl-template-assert t] ["Attribute (Decl)" vhdl-template-attribute-decl t] ["Attribute (Spec)" vhdl-template-attribute-spec t] ["Block" vhdl-template-block t] ["Case" vhdl-template-case-is t] ["Component (Decl)" vhdl-template-component-decl t] ["(Component) Instance" vhdl-template-component-inst t] ["Conditional (Signal Asst)" vhdl-template-conditional-signal-asst t] ["Configuration (Block)" vhdl-template-block-configuration t] ["Configuration (Comp)" vhdl-template-component-conf t] ["Configuration (Decl)" vhdl-template-configuration-decl t] ["Configuration (Spec)" vhdl-template-configuration-spec t] ["Constant" vhdl-template-constant t] ["Disconnect" vhdl-template-disconnect t] ["Else" vhdl-template-else t] ["Elsif" vhdl-template-elsif t] ["Entity" vhdl-template-entity t] ["Exit" vhdl-template-exit t] ["File" vhdl-template-file t] ["For (Generate)" vhdl-template-for-generate t] ["For (Loop)" vhdl-template-for-loop t] ["Function (Body)" vhdl-template-function-body t] ["Function (Decl)" vhdl-template-function-decl t] ["Generic" vhdl-template-generic t] ["Group (Decl)" vhdl-template-group-decl t] ["Group (Template)" vhdl-template-group-template t]) ("VHDL Construct 2" ["If (Generate)" vhdl-template-if-generate t] ["If (Then)" vhdl-template-if-then t] ["Library" vhdl-template-library t] ["Loop" vhdl-template-bare-loop t] ["Map" vhdl-template-map t] ["Next" vhdl-template-next t] ["Others (Aggregate)" vhdl-template-others t] ["Package (Decl)" vhdl-template-package-decl t] ["Package (Body)" vhdl-template-package-body t] ["Port" vhdl-template-port t] ["Procedure (Body)" vhdl-template-procedure-body t] ["Procedure (Decl)" vhdl-template-procedure-decl t] ["Process (Comb)" vhdl-template-process-comb t] ["Process (Seq)" vhdl-template-process-seq t] ["Report" vhdl-template-report t] ["Return" vhdl-template-return t] ["Select" vhdl-template-selected-signal-asst t] ["Signal" vhdl-template-signal t] ["Subtype" vhdl-template-subtype t] ["Type" vhdl-template-type t] ["Use" vhdl-template-use t] ["Variable" vhdl-template-variable t] ["Wait" vhdl-template-wait t] ["(Clocked Wait)" vhdl-template-clocked-wait t] ["When" vhdl-template-when t] ["While (Loop)" vhdl-template-while-loop t] ["With" vhdl-template-with t])) vhdl-standard-p ams (("VHDL-AMS Construct" ["Break" vhdl-template-break t] ["Case (Use)" vhdl-template-case-use t] ["If (Use)" vhdl-template-if-use t] ["Limit" vhdl-template-limit t] ["Nature" vhdl-template-nature t] ["Procedural" vhdl-template-procedural t] ["Quantity (Free)" vhdl-template-quantity-free t] ["Quantity (Branch)" vhdl-template-quantity-branch t] ["Quantity (Source)" vhdl-template-quantity-source t] ["Subnature" vhdl-template-subnature t] ["Terminal" vhdl-template-terminal t])) (["Insert Construct..." vhdl-template-insert-construct :keys "C-c C-i C-t"] "--") ("Package") (["numeric_bit" vhdl-template-package-numeric-bit t] ["numeric_std" vhdl-template-package-numeric-std t] ["std_logic_1164" vhdl-template-package-std-logic-1164 t] ["textio" vhdl-template-package-textio t] "--" ["std_logic_arith" vhdl-template-package-std-logic-arith t] ["std_logic_signed" vhdl-template-package-std-logic-signed t] ["std_logic_unsigned" vhdl-template-package-std-logic-unsigned t] ["std_logic_misc" vhdl-template-package-std-logic-misc t] ["std_logic_textio" vhdl-template-package-std-logic-textio t] "--") (["fundamental_constants" vhdl-template-package-fundamental-constants t] ["material_constants" vhdl-template-package-material-constants t] ["energy_systems" vhdl-template-package-energy-systems t] ["electrical_systems" vhdl-template-package-electrical-systems t] ["mechanical_systems" vhdl-template-package-mechanical-systems t] ["radiant_systems" vhdl-template-package-radiant-systems t] ["thermal_systems" vhdl-template-package-thermal-systems t] ["fluidic_systems" vhdl-template-package-fluidic-systems t] "--") math (["math_complex" vhdl-template-package-math-complex t] ["math_real" vhdl-template-package-math-real t] "--") (["Insert Package..." vhdl-template-insert-package :keys "C-c C-i C-p"]) (("Directive" ["translate_on" vhdl-template-directive-translate-on t] ["translate_off" vhdl-template-directive-translate-off t] ["synthesis_on" vhdl-template-directive-synthesis-on t] ["synthesis_off" vhdl-template-directive-synthesis-off t] "--" ["Insert Directive..." vhdl-template-insert-directive :keys "C-c C-i C-d"]) "--" ["Insert Header" vhdl-template-header :keys "C-c C-t C-h"] ["Insert Footer" vhdl-template-footer t] ["Insert Date" vhdl-template-insert-date t] ["Modify Date" vhdl-template-modify :keys "C-c C-t C-m"] "--" ["Query Next Prompt" vhdl-template-search-prompt t]) ("Model") vhdl-function-name "vhdl-model" :keys "C-c C-m " key-description 2 "Model" ("--" "--" ["Insert Model..." vhdl-model-insert :keys "C-c C-i C-m"] ["Customize Model..." (customize-option 'vhdl-model-alist) t]) ("Port" ["Copy" vhdl-port-copy t] "--" ["Paste As Entity" vhdl-port-paste-entity vhdl-port-list] ["Paste As Component" vhdl-port-paste-component vhdl-port-list] ["Paste As Instance" vhdl-port-paste-instance :keys "C-c C-p C-i" :active vhdl-port-list] ["Paste As Signals" vhdl-port-paste-signals vhdl-port-list] ["Paste As Constants" vhdl-port-paste-constants vhdl-port-list] ["Paste As Generic Map" vhdl-port-paste-generic-map vhdl-port-list] ["Paste As Initializations" vhdl-port-paste-initializations vhdl-port-list] "--" ["Paste As Testbench" vhdl-port-paste-testbench vhdl-port-list] "--" ["Flatten" vhdl-port-flatten :style toggle :selected vhdl-port-flattened :active vhdl-port-list] ["Reverse Direction" vhdl-port-reverse-direction :style toggle :selected vhdl-port-reversed-direction :active vhdl-port-list]) ("Compose" ["New Component" vhdl-compose-new-component t] ["Copy Component" vhdl-port-copy t] ["Place Component" vhdl-compose-place-component vhdl-port-list] ["Wire Components" vhdl-compose-wire-components t] "--" ["Generate Configuration" vhdl-compose-configuration t] ["Generate Components Package" vhdl-compose-components-package t]) ("Subprogram" ["Copy" vhdl-subprog-copy t] "--" ["Paste As Declaration" vhdl-subprog-paste-declaration vhdl-subprog-list] ["Paste As Body" vhdl-subprog-paste-body vhdl-subprog-list] ["Paste As Call" vhdl-subprog-paste-call vhdl-subprog-list] "--" ["Flatten" vhdl-subprog-flatten :style toggle :selected vhdl-subprog-flattened :active vhdl-subprog-list]) ("Comment" ["(Un)Comment Out Region" vhdl-comment-uncomment-region (mark)] "--" ["Insert Inline Comment" vhdl-comment-append-inline t] ["Insert Horizontal Line" vhdl-comment-display-line t] ["Insert Display Comment" vhdl-comment-display t] "--" ["Fill Comment" fill-paragraph t] ["Fill Comment Region" fill-region (mark)] ["Kill Comment Region" vhdl-comment-kill-region (mark)] ["Kill Inline Comment Region" vhdl-comment-kill-inline-region (mark)]) ("Line" ["Kill" vhdl-line-kill t] ["Copy" vhdl-line-copy t] ["Yank" vhdl-line-yank t] ["Expand" vhdl-line-expand t] "--" ["Transpose Next" vhdl-line-transpose-next t] ["Transpose Prev" vhdl-line-transpose-previous t] ["Open" vhdl-line-open t] ["Join" vhdl-delete-indentation t] "--" ["Goto" goto-line t] ["(Un)Comment Out" vhdl-comment-uncomment-line t]) ("Move" ["Forward Statement" vhdl-end-of-statement t] ["Backward Statement" vhdl-beginning-of-statement t] ["Forward Expression" vhdl-forward-sexp t] ["Backward Expression" vhdl-backward-sexp t] ["Forward Same Indent" vhdl-forward-same-indent t] ["Backward Same Indent" vhdl-backward-same-indent t] ["Forward Function" vhdl-end-of-defun t] ["Backward Function" vhdl-beginning-of-defun t] ["Mark Function" vhdl-mark-defun t]) vhdl-compiler-alist comp-alist vhdl-model-alist model model-alist ("Indent" ["Line" indent-according-to-mode :keys "C-c C-i C-l"] ["Group" vhdl-indent-group :keys "C-c C-i C-g"] ["Region" vhdl-indent-region (mark)] ["Buffer" vhdl-indent-buffer :keys "C-c C-i C-b"]) ("Align" ["Group" vhdl-align-group t] ["Same Indent" vhdl-align-same-indent :keys "C-c C-a C-i"] ["List" vhdl-align-list t] ["Declarations" vhdl-align-declarations t] ["Region" vhdl-align-region (mark)] ["Buffer" vhdl-align-buffer t] "--" ["Inline Comment Group" vhdl-align-inline-comment-group t] ["Inline Comment Region" vhdl-align-inline-comment-region (mark)] ["Inline Comment Buffer" vhdl-align-inline-comment-buffer t]) ("Fill" ["List" vhdl-fill-list t] ["Group" vhdl-fill-group t] ["Same Indent" vhdl-fill-same-indent :keys "C-c C-f C-i"] ["Region" vhdl-fill-region (mark)]) ("Beautify" ["Region" vhdl-beautify-region (mark)] ["Buffer" vhdl-beautify-buffer t]) ("Fix" ["Generic/Port Clause" vhdl-fix-clause t] ["Generic/Port Clause Buffer" vhdl-fix-clause t] "--" ["Case Region" vhdl-fix-case-region (mark)] ["Case Buffer" vhdl-fix-case-buffer t] "--" ["Whitespace Region" vhdl-fixup-whitespace-region (mark)] ["Whitespace Buffer" vhdl-fixup-whitespace-buffer t] "--" ["Trailing Spaces Buffer" vhdl-remove-trailing-spaces t]) ("Update" ["Sensitivity List" vhdl-update-sensitivity-list-process t] ["Sensitivity List Buffer" vhdl-update-sensitivity-list-buffer t]) ["Fontify Buffer" vhdl-fontify-buffer t] ["Statistics Buffer" vhdl-statistics-buffer t] ["Show Messages" vhdl-show-messages t] ["Syntactic Info" vhdl-show-syntactic-information t] ["Speedbar" vhdl-speedbar t] ["Hide/Show" vhdl-hs-minor-mode t] ("Documentation" ["VHDL Mode" vhdl-doc-mode :keys "C-c C-h"] ["Release Notes" (vhdl-doc-variable 'vhdl-doc-release-notes) t] ["Reserved Words" (vhdl-doc-variable 'vhdl-doc-keywords) t] ["Coding Style" (vhdl-doc-variable 'vhdl-doc-coding-style) t]) ["Version" vhdl-version t] ["Bug Report..." vhdl-submit-bug-report t] "Options" ("Mode" ["Electric Mode" (progn (customize-set-variable 'vhdl-electric-mode (not vhdl-electric-mode)) (vhdl-mode-line-update)) :style toggle :selected vhdl-electric-mode :keys "C-c C-m C-e"] ["Stutter Mode" (progn (customize-set-variable 'vhdl-stutter-mode (not vhdl-stutter-mode)) (vhdl-mode-line-update)) :style toggle :selected vhdl-stutter-mode :keys "C-c C-m C-s"] ["Indent Tabs Mode" (progn (customize-set-variable 'vhdl-indent-tabs-mode (not vhdl-indent-tabs-mode)) (setq indent-tabs-mode vhdl-indent-tabs-mode)) :style toggle :selected vhdl-indent-tabs-mode] "--" ["Customize Group..." (customize-group 'vhdl-mode) t]) ["Project Setup..." (customize-option 'vhdl-project-alist) t] ("Selected Project at Startup" ["None" (progn (customize-set-variable 'vhdl-project nil) (vhdl-set-project #1#)) :style radio :selected (null vhdl-project)] "--") progn customize-set-variable 'vhdl-project (vhdl-project) (["Setup File Name..." (customize-option 'vhdl-project-file-name) t] ("Auto Load Setup File" ["At Startup" (customize-set-variable 'vhdl-project-auto-load (if (memq 'startup vhdl-project-auto-load) (delq 'startup vhdl-project-auto-load) (cons 'startup vhdl-project-auto-load))) :style toggle :selected (memq 'startup vhdl-project-auto-load)]) ["Sort Projects" (customize-set-variable 'vhdl-project-sort (not vhdl-project-sort)) :style toggle :selected vhdl-project-sort] "--" ["Customize Group..." (customize-group 'vhdl-project) t]) ["Compiler Setup..." (customize-option 'vhdl-compiler-alist) t] ("Selected Compiler at Startup") 'vhdl-compiler (vhdl-compiler) (["Use Local Error Regexp" (customize-set-variable 'vhdl-compile-use-local-error-regexp (not vhdl-compile-use-local-error-regexp)) :style toggle :selected vhdl-compile-use-local-error-regexp] ["Makefile Default Targets..." (customize-option 'vhdl-makefile-default-targets) t] ["Makefile Generation Hook..." (customize-option 'vhdl-makefile-generation-hook) t] ["Default Library Name" (customize-option 'vhdl-default-library) t] "--" ["Customize Group..." (customize-group 'vhdl-compiler) t]) (("Style" ("VHDL Standard" ["VHDL'87" (progn (customize-set-variable 'vhdl-standard (list '87 (cadr vhdl-standard))) (vhdl-activate-customizations)) :style radio :selected (eq '87 (car vhdl-standard))] ["VHDL'93/02" (progn (customize-set-variable 'vhdl-standard (list '93 (cadr vhdl-standard))) (vhdl-activate-customizations)) :style radio :selected (eq '93 (car vhdl-standard))] "--" ["VHDL-AMS" (progn (customize-set-variable 'vhdl-standard (list (car vhdl-standard) (if (memq 'ams (cadr vhdl-standard)) (delq 'ams (cadr vhdl-standard)) (cons 'ams (cadr vhdl-standard))))) (vhdl-activate-customizations)) :style toggle :selected (memq 'ams (cadr vhdl-standard))] ["Math Packages" (progn (customize-set-variable 'vhdl-standard (list (car vhdl-standard) (if (memq 'math (cadr vhdl-standard)) (delq 'math (cadr vhdl-standard)) (cons 'math (cadr vhdl-standard))))) (vhdl-activate-customizations)) :style toggle :selected (memq 'math (cadr vhdl-standard))]) ["Indentation Offset..." (customize-option 'vhdl-basic-offset) t] ["Upper Case Keywords" (customize-set-variable 'vhdl-upper-case-keywords (not vhdl-upper-case-keywords)) :style toggle :selected vhdl-upper-case-keywords] ["Upper Case Types" (customize-set-variable 'vhdl-upper-case-types (not vhdl-upper-case-types)) :style toggle :selected vhdl-upper-case-types] ["Upper Case Attributes" (customize-set-variable 'vhdl-upper-case-attributes (not vhdl-upper-case-attributes)) :style toggle :selected vhdl-upper-case-attributes] ["Upper Case Enumeration Values" (customize-set-variable 'vhdl-upper-case-enum-values (not vhdl-upper-case-enum-values)) :style toggle :selected vhdl-upper-case-enum-values] ["Upper Case Constants" (customize-set-variable 'vhdl-upper-case-constants (not vhdl-upper-case-constants)) :style toggle :selected vhdl-upper-case-constants] ("Use Direct Instantiation" ["Never" (customize-set-variable 'vhdl-use-direct-instantiation 'never) :style radio :selected (eq 'never vhdl-use-direct-instantiation)] ["Standard" (customize-set-variable 'vhdl-use-direct-instantiation 'standard) :style radio :selected (eq 'standard vhdl-use-direct-instantiation)] ["Always" (customize-set-variable 'vhdl-use-direct-instantiation 'always) :style radio :selected (eq 'always vhdl-use-direct-instantiation)]) ["Include Array Index and Record Field in Sensitivity List" (customize-set-variable 'vhdl-array-index-record-field-in-sensitivity-list (not vhdl-array-index-record-field-in-sensitivity-list)) :style toggle :selected vhdl-array-index-record-field-in-sensitivity-list] "--" ["Customize Group..." (customize-group 'vhdl-style) t]) ("Naming" ["Entity File Name..." (customize-option 'vhdl-entity-file-name) t] ["Architecture File Name..." (customize-option 'vhdl-architecture-file-name) t] ["Configuration File Name..." (customize-option 'vhdl-configuration-file-name) t] ["Package File Name..." (customize-option 'vhdl-package-file-name) t] ("File Name Case" ["As Is" (customize-set-variable 'vhdl-file-name-case 'identity) :style radio :selected (eq 'identity vhdl-file-name-case)] ["Lower Case" (customize-set-variable 'vhdl-file-name-case 'downcase) :style radio :selected (eq 'downcase vhdl-file-name-case)] ["Upper Case" (customize-set-variable 'vhdl-file-name-case 'upcase) :style radio :selected (eq 'upcase vhdl-file-name-case)] ["Capitalize" (customize-set-variable 'vhdl-file-name-case 'capitalize) :style radio :selected (eq 'capitalize vhdl-file-name-case)]) "--" ["Customize Group..." (customize-group 'vhdl-naming) t]) ("Template" ("Electric Keywords" ["VHDL Keywords" (customize-set-variable 'vhdl-electric-keywords (if (memq 'vhdl vhdl-electric-keywords) (delq 'vhdl vhdl-electric-keywords) (cons 'vhdl vhdl-electric-keywords))) :style toggle :selected (memq 'vhdl vhdl-electric-keywords)] ["User Model Keywords" (customize-set-variable 'vhdl-electric-keywords (if (memq 'user vhdl-electric-keywords) (delq 'user vhdl-electric-keywords) (cons 'user vhdl-electric-keywords))) :style toggle :selected (memq 'user vhdl-electric-keywords)]) ("Insert Optional Labels" ["None" (customize-set-variable 'vhdl-optional-labels 'none) :style radio :selected (eq 'none vhdl-optional-labels)] ["Processes Only" (customize-set-variable 'vhdl-optional-labels 'process) :style radio :selected (eq 'process vhdl-optional-labels)] ["All Constructs" (customize-set-variable 'vhdl-optional-labels 'all) :style radio :selected (eq 'all vhdl-optional-labels)]) ("Insert Empty Lines" ["None" (customize-set-variable 'vhdl-insert-empty-lines 'none) :style radio :selected (eq 'none vhdl-insert-empty-lines)] ["Design Units Only" (customize-set-variable 'vhdl-insert-empty-lines 'unit) :style radio :selected (eq 'unit vhdl-insert-empty-lines)] ["All Constructs" (customize-set-variable 'vhdl-insert-empty-lines 'all) :style radio :selected (eq 'all vhdl-insert-empty-lines)]) ["Argument List Indent" (customize-set-variable 'vhdl-argument-list-indent (not vhdl-argument-list-indent)) :style toggle :selected vhdl-argument-list-indent] ["Association List with Formals" (customize-set-variable 'vhdl-association-list-with-formals (not vhdl-association-list-with-formals)) :style toggle :selected vhdl-association-list-with-formals] ["Conditions in Parenthesis" (customize-set-variable 'vhdl-conditions-in-parenthesis (not vhdl-conditions-in-parenthesis)) :style toggle :selected vhdl-conditions-in-parenthesis] ["Zero String..." (customize-option 'vhdl-zero-string) t] ["One String..." (customize-option 'vhdl-one-string) t] ("File Header" ["Header String..." (customize-option 'vhdl-file-header) t] ["Footer String..." (customize-option 'vhdl-file-footer) t] ["Company Name..." (customize-option 'vhdl-company-name) t] ["Copyright String..." (customize-option 'vhdl-copyright-string) t] ["Platform Specification..." (customize-option 'vhdl-platform-spec) t] ["Date Format..." (customize-option 'vhdl-date-format) t] ["Modify Date Prefix String..." (customize-option 'vhdl-modify-date-prefix-string) t] ["Modify Date on Saving" (progn (customize-set-variable 'vhdl-modify-date-on-saving (not vhdl-modify-date-on-saving)) (vhdl-activate-customizations)) :style toggle :selected vhdl-modify-date-on-saving]) ("Sequential Process" ("Kind of Reset" ["None" (customize-set-variable 'vhdl-reset-kind 'none) :style radio :selected (eq 'none vhdl-reset-kind)] ["Synchronous" (customize-set-variable 'vhdl-reset-kind 'sync) :style radio :selected (eq 'sync vhdl-reset-kind)] ["Asynchronous" (customize-set-variable 'vhdl-reset-kind 'async) :style radio :selected (eq 'async vhdl-reset-kind)] ["Query" (customize-set-variable 'vhdl-reset-kind 'query) :style radio :selected (eq 'query vhdl-reset-kind)]) ["Reset is Active High" (customize-set-variable 'vhdl-reset-active-high (not vhdl-reset-active-high)) :style toggle :selected vhdl-reset-active-high] ["Use Rising Clock Edge" (customize-set-variable 'vhdl-clock-rising-edge (not vhdl-clock-rising-edge)) :style toggle :selected vhdl-clock-rising-edge] ("Clock Edge Condition" ["Standard" (customize-set-variable 'vhdl-clock-edge-condition 'standard) :style radio :selected (eq 'standard vhdl-clock-edge-condition)] ["Function \"rising_edge\"" (customize-set-variable 'vhdl-clock-edge-condition 'function) :style radio :selected (eq 'function vhdl-clock-edge-condition)]) ["Clock Name..." (customize-option 'vhdl-clock-name) t] ["Reset Name..." (customize-option 'vhdl-reset-name) t]) "--" ["Customize Group..." (customize-group 'vhdl-template) t]) ("Model" ["Model Definition..." (customize-option 'vhdl-model-alist) t]) ("Port" ["Include Port Comments" (customize-set-variable 'vhdl-include-port-comments (not vhdl-include-port-comments)) :style toggle :selected vhdl-include-port-comments] ["Include Direction Comments" (customize-set-variable 'vhdl-include-direction-comments (not vhdl-include-direction-comments)) :style toggle :selected vhdl-include-direction-comments] ["Include Type Comments" (customize-set-variable 'vhdl-include-type-comments (not vhdl-include-type-comments)) :style toggle :selected vhdl-include-type-comments] ("Include Group Comments" ["Never" (customize-set-variable 'vhdl-include-group-comments 'never) :style radio :selected (eq 'never vhdl-include-group-comments)] ["Declarations" (customize-set-variable 'vhdl-include-group-comments 'decl) :style radio :selected (eq 'decl vhdl-include-group-comments)] ["Always" (customize-set-variable 'vhdl-include-group-comments 'always) :style radio :selected (eq 'always vhdl-include-group-comments)]) ["Actual Port Name..." (customize-option 'vhdl-actual-port-name) t] ["Instance Name..." (customize-option 'vhdl-instance-name) t] ("Testbench" ["Entity Name..." (customize-option 'vhdl-testbench-entity-name) t] ["Architecture Name..." (customize-option 'vhdl-testbench-architecture-name) t] ["Configuration Name..." (customize-option 'vhdl-testbench-configuration-name) t] ["DUT Name..." (customize-option 'vhdl-testbench-dut-name) t] ["Include Header" (customize-set-variable 'vhdl-testbench-include-header (not vhdl-testbench-include-header)) :style toggle :selected vhdl-testbench-include-header] ["Declarations..." (customize-option 'vhdl-testbench-declarations) t] ["Statements..." (customize-option 'vhdl-testbench-statements) t] ["Initialize Signals" (customize-set-variable 'vhdl-testbench-initialize-signals (not vhdl-testbench-initialize-signals)) :style toggle :selected vhdl-testbench-initialize-signals] ["Include Library Clause" (customize-set-variable 'vhdl-testbench-include-library (not vhdl-testbench-include-library)) :style toggle :selected vhdl-testbench-include-library] ["Include Configuration" (customize-set-variable 'vhdl-testbench-include-configuration (not vhdl-testbench-include-configuration)) :style toggle :selected vhdl-testbench-include-configuration] ("Create Files" ["None" (customize-set-variable 'vhdl-testbench-create-files 'none) :style radio :selected (eq 'none vhdl-testbench-create-files)] ["Single" (customize-set-variable 'vhdl-testbench-create-files 'single) :style radio :selected (eq 'single vhdl-testbench-create-files)] ["Separate" (customize-set-variable 'vhdl-testbench-create-files 'separate) :style radio :selected (eq 'separate vhdl-testbench-create-files)]) ["Testbench Entity File Name..." (customize-option 'vhdl-testbench-entity-file-name) t] ["Testbench Architecture File Name..." (customize-option 'vhdl-testbench-architecture-file-name) t]) "--" ["Customize Group..." (customize-group 'vhdl-port) t]) ("Compose" ["Architecture Name..." (customize-option 'vhdl-compose-architecture-name) t] ["Configuration Name..." (customize-option 'vhdl-compose-configuration-name) t] ["Components Package Name..." (customize-option 'vhdl-components-package-name) t] ["Use Components Package" (customize-set-variable 'vhdl-use-components-package (not vhdl-use-components-package)) :style toggle :selected vhdl-use-components-package] ["Include Header" (customize-set-variable 'vhdl-compose-include-header (not vhdl-compose-include-header)) :style toggle :selected vhdl-compose-include-header] ("Create Entity/Architecture Files" ["None" (customize-set-variable 'vhdl-compose-create-files 'none) :style radio :selected (eq 'none vhdl-compose-create-files)] ["Single" (customize-set-variable 'vhdl-compose-create-files 'single) :style radio :selected (eq 'single vhdl-compose-create-files)] ["Separate" (customize-set-variable 'vhdl-compose-create-files 'separate) :style radio :selected (eq 'separate vhdl-compose-create-files)]) ["Create Configuration File" (customize-set-variable 'vhdl-compose-configuration-create-file (not vhdl-compose-configuration-create-file)) :style toggle :selected vhdl-compose-configuration-create-file] ["Hierarchical Configuration" (customize-set-variable 'vhdl-compose-configuration-hierarchical (not vhdl-compose-configuration-hierarchical)) :style toggle :selected vhdl-compose-configuration-hierarchical] ["Use Subconfiguration" (customize-set-variable 'vhdl-compose-configuration-use-subconfiguration (not vhdl-compose-configuration-use-subconfiguration)) :style toggle :selected vhdl-compose-configuration-use-subconfiguration] "--" ["Customize Group..." (customize-group 'vhdl-compose) t]) ("Comment" ["Self Insert Comments" (customize-set-variable 'vhdl-self-insert-comments (not vhdl-self-insert-comments)) :style toggle :selected vhdl-self-insert-comments] ["Prompt for Comments" (customize-set-variable 'vhdl-prompt-for-comments (not vhdl-prompt-for-comments)) :style toggle :selected vhdl-prompt-for-comments] ["Inline Comment Column..." (customize-option 'vhdl-inline-comment-column) t] ["End Comment Column..." (customize-option 'vhdl-end-comment-column) t] "--" ["Customize Group..." (customize-group 'vhdl-comment) t]) ("Align" ["Auto Align Templates" (customize-set-variable 'vhdl-auto-align (not vhdl-auto-align)) :style toggle :selected vhdl-auto-align] ["Align Line Groups" (customize-set-variable 'vhdl-align-groups (not vhdl-align-groups)) :style toggle :selected vhdl-align-groups] ["Group Separation String..." (customize-set-variable 'vhdl-align-group-separate) t] ["Align Lines with Same Indent" (customize-set-variable 'vhdl-align-same-indent (not vhdl-align-same-indent)) :style toggle :selected vhdl-align-same-indent] "--" ["Customize Group..." (customize-group 'vhdl-align) t]) ("Highlight" ["Highlighting On/Off..." (customize-option (if (fboundp 'global-font-lock-mode) 'global-font-lock-mode 'font-lock-auto-fontify)) t] ["Highlight Keywords" (progn (customize-set-variable 'vhdl-highlight-keywords (not vhdl-highlight-keywords)) (vhdl-fontify-buffer)) :style toggle :selected vhdl-highlight-keywords] ["Highlight Names" (progn (customize-set-variable 'vhdl-highlight-names (not vhdl-highlight-names)) (vhdl-fontify-buffer)) :style toggle :selected vhdl-highlight-names] ["Highlight Special Words" (progn (customize-set-variable 'vhdl-highlight-special-words (not vhdl-highlight-special-words)) (vhdl-fontify-buffer)) :style toggle :selected vhdl-highlight-special-words] ["Highlight Forbidden Words" (progn (customize-set-variable 'vhdl-highlight-forbidden-words (not vhdl-highlight-forbidden-words)) (vhdl-fontify-buffer)) :style toggle :selected vhdl-highlight-forbidden-words] ["Highlight Verilog Keywords" (progn (customize-set-variable 'vhdl-highlight-verilog-keywords (not vhdl-highlight-verilog-keywords)) (vhdl-fontify-buffer)) :style toggle :selected vhdl-highlight-verilog-keywords] ["Highlight \"translate_off\"" (progn (customize-set-variable 'vhdl-highlight-translate-off (not vhdl-highlight-translate-off)) (vhdl-fontify-buffer)) :style toggle :selected vhdl-highlight-translate-off] ["Case Sensitive Highlighting" (progn (customize-set-variable 'vhdl-highlight-case-sensitive (not vhdl-highlight-case-sensitive)) (vhdl-fontify-buffer)) :style toggle :selected vhdl-highlight-case-sensitive] ["Special Syntax Definition..." (customize-option 'vhdl-special-syntax-alist) t] ["Forbidden Words..." (customize-option 'vhdl-forbidden-words) t] ["Forbidden Syntax..." (customize-option 'vhdl-forbidden-syntax) t] ["Directive Keywords..." (customize-option 'vhdl-directive-keywords) t] ["Colors..." (customize-group 'vhdl-highlight-faces) t] "--" ["Customize Group..." (customize-group 'vhdl-highlight) t]) ("Speedbar" ["Auto Open at Startup" (customize-set-variable 'vhdl-speedbar-auto-open (not vhdl-speedbar-auto-open)) :style toggle :selected vhdl-speedbar-auto-open] ("Default Displaying Mode" ["Files" (customize-set-variable 'vhdl-speedbar-display-mode 'files) :style radio :selected (eq 'files vhdl-speedbar-display-mode)] ["Directory Hierarchy" (customize-set-variable 'vhdl-speedbar-display-mode 'directory) :style radio :selected (eq 'directory vhdl-speedbar-display-mode)] ["Project Hierarchy" (customize-set-variable 'vhdl-speedbar-display-mode 'project) :style radio :selected (eq 'project vhdl-speedbar-display-mode)]) ["Indentation Offset..." (customize-option 'speedbar-indentation-width) t] ["Scan Size Limits..." (customize-option 'vhdl-speedbar-scan-limit) t] ["Jump to Unit when Opening" (customize-set-variable 'vhdl-speedbar-jump-to-unit (not vhdl-speedbar-jump-to-unit)) :style toggle :selected vhdl-speedbar-jump-to-unit] ["Update Hierarchy on File Saving" (customize-set-variable 'vhdl-speedbar-update-on-saving (not vhdl-speedbar-update-on-saving)) :style toggle :selected vhdl-speedbar-update-on-saving] ("Save in Cache File" ["Hierarchy Information" (customize-set-variable 'vhdl-speedbar-save-cache (if (memq 'hierarchy vhdl-speedbar-save-cache) (delq 'hierarchy vhdl-speedbar-save-cache) (cons 'hierarchy vhdl-speedbar-save-cache))) :style toggle :selected (memq 'hierarchy vhdl-speedbar-save-cache)] ["Displaying Status" (customize-set-variable 'vhdl-speedbar-save-cache (if (memq 'display vhdl-speedbar-save-cache) (delq 'display vhdl-speedbar-save-cache) (cons 'display vhdl-speedbar-save-cache))) :style toggle :selected (memq 'display vhdl-speedbar-save-cache)]) ["Cache File Name..." (customize-option 'vhdl-speedbar-cache-file-name) t] "--" ["Customize Group..." (customize-group 'vhdl-speedbar) t]) ("Menu" ["Add Index Menu when Loading File" (progn (customize-set-variable 'vhdl-index-menu (not vhdl-index-menu)) (vhdl-index-menu-init)) :style toggle :selected vhdl-index-menu] ["Add Source File Menu when Loading File" (progn (customize-set-variable 'vhdl-source-file-menu (not vhdl-source-file-menu)) (vhdl-add-source-files-menu)) :style toggle :selected vhdl-source-file-menu] ["Add Hideshow Menu at Startup" (progn (customize-set-variable 'vhdl-hideshow-menu (not vhdl-hideshow-menu)) (vhdl-activate-customizations)) :style toggle :selected vhdl-hideshow-menu] ["Hide Everything Initially" (customize-set-variable 'vhdl-hide-all-init (not vhdl-hide-all-init)) :style toggle :selected vhdl-hide-all-init] "--" ["Customize Group..." (customize-group 'vhdl-menu) t]) ("Print" ["In Two Column Format" (progn (customize-set-variable 'vhdl-print-two-column (not vhdl-print-two-column)) (message "Activate new setting by saving options and restarting Emacs")) :style toggle :selected vhdl-print-two-column] ["Use Customized Faces" (progn (customize-set-variable 'vhdl-print-customize-faces (not vhdl-print-customize-faces)) (message "Activate new setting by saving options and restarting Emacs")) :style toggle :selected vhdl-print-customize-faces] "--" ["Customize Group..." (customize-group 'vhdl-print) t]) ("Miscellaneous" ["Use Intelligent Tab" (progn (customize-set-variable 'vhdl-intelligent-tab (not vhdl-intelligent-tab)) (vhdl-activate-customizations)) :style toggle :selected vhdl-intelligent-tab] ["Indent Syntax-Based" (customize-set-variable 'vhdl-indent-syntax-based (not vhdl-indent-syntax-based)) :style toggle :selected vhdl-indent-syntax-based] ["Indent Comments Like Next Code Line" (customize-set-variable 'vhdl-indent-comment-like-next-code-line (not vhdl-indent-comment-like-next-code-line)) :style toggle :selected vhdl-indent-comment-like-next-code-line] ["Word Completion is Case Sensitive" (customize-set-variable 'vhdl-word-completion-case-sensitive (not vhdl-word-completion-case-sensitive)) :style toggle :selected vhdl-word-completion-case-sensitive] ["Word Completion in Minibuffer" (progn (customize-set-variable 'vhdl-word-completion-in-minibuffer (not vhdl-word-completion-in-minibuffer)) (message "Activate new setting by saving options and restarting Emacs")) :style toggle :selected vhdl-word-completion-in-minibuffer] ["Underscore is Part of Word" (progn (customize-set-variable 'vhdl-underscore-is-part-of-word (not vhdl-underscore-is-part-of-word)) (vhdl-activate-customizations)) :style toggle :selected vhdl-underscore-is-part-of-word] "--" ["Customize Group..." (customize-group 'vhdl-misc) t]) ["Related..." (customize-browse 'vhdl-related) t] "--" ["Save Options" customize-save-customized t] ["Activate Options" vhdl-activate-customizations t] ["Browse Options..." vhdl-customize t])] 51 (#$ . 110630)])
#@17 VHDL Mode menu.
(defvar vhdl-mode-menu-list (vhdl-create-mode-menu) (#$ . 144552))
#@24 Update VHDL Mode menu.
(defalias 'vhdl-update-mode-menu #[nil "\302!\210\303 \304!\210\305\306!\210\307\310	\311$\207" [vhdl-mode-menu-list vhdl-mode-map easy-menu-remove vhdl-create-mode-menu easy-menu-add (lambda (#1=#:def-tmp-var) (defvar vhdl-mode-menu #1# #2="Menu keymap for VHDL Mode.")) nil easy-menu-do-define vhdl-mode-menu #2#] 5 (#$ . 144641) nil])
#@74 Imenu generic expression for VHDL Mode.  See `imenu-generic-expression'.
(defconst vhdl-imenu-generic-expression '(("Subprogram" "^\\s-*\\(\\(\\(impure\\|pure\\)\\s-+\\|\\)function\\|procedure\\)\\s-+\\(\"?\\(\\w\\|\\s_\\)+\"?\\)" 4) ("Instance" "^\\s-*\\(\\(\\w\\|\\s_\\)+\\s-*:\\(\\s-\\|\n\\)*\\(entity\\s-+\\(\\w\\|\\s_\\)+\\.\\)?\\(\\w\\|\\s_\\)+\\)\\(\\s-\\|\n\\)+\\(generic\\|port\\)\\s-+map\\>" 1) ("Component" "^\\s-*\\(component\\)\\s-+\\(\\(\\w\\|\\s_\\)+\\)" 2) ("Procedural" "^\\s-*\\(\\(\\w\\|\\s_\\)+\\)\\s-*:\\(\\s-\\|\n\\)*\\(procedural\\)" 1) ("Process" "^\\s-*\\(\\(\\w\\|\\s_\\)+\\)\\s-*:\\(\\s-\\|\n\\)*\\(\\(postponed\\s-+\\|\\)process\\)" 1) ("Block" "^\\s-*\\(\\(\\w\\|\\s_\\)+\\)\\s-*:\\(\\s-\\|\n\\)*\\(block\\)" 1) ("Package" "^\\s-*\\(package\\( body\\|\\)\\)\\s-+\\(\\(\\w\\|\\s_\\)+\\)" 3) ("Configuration" "^\\s-*\\(configuration\\)\\s-+\\(\\(\\w\\|\\s_\\)+\\s-+of\\s-+\\(\\w\\|\\s_\\)+\\)" 2) ("Architecture" "^\\s-*\\(architecture\\)\\s-+\\(\\(\\w\\|\\s_\\)+\\s-+of\\s-+\\(\\w\\|\\s_\\)+\\)" 2) ("Entity" "^\\s-*\\(entity\\)\\s-+\\(\\(\\w\\|\\s_\\)+\\)" 2)) (#$ . 145012))
#@24 Initialize index menu.
(defalias 'vhdl-index-menu-init #[nil "\304\300!\210\305\304\302!\210	\205\306\307!\205\310\311!\207" [imenu-case-fold-search vhdl-imenu-generic-expression imenu-generic-expression vhdl-index-menu make-local-variable t fboundp imenu imenu-add-to-menubar "Index"] 2 (#$ . 146123)])
(defvar vhdl-sources-menu nil)
#@79 Call `directory-files' if DIRECTORY exists, otherwise generate error
message.
(defalias 'vhdl-directory-files #[(directory &optional full match) "\304!\204\305\306\"\207\307	\n#\310\311\"\310\312\"\211)\207" [directory full match dir file-directory-p vhdl-warning-when-idle "No such directory: \"%s\"" directory-files delete "." ".."] 5 (#$ . 146471)])
#@66 Get list of VHDL source files in DIRECTORY or current directory.
(defalias 'vhdl-get-source-files #[(&optional full directory) "\306\307\n\203&\n\211@A)\310=\203	\n\211@@)\311Q\nA\211\204\n	\312\313\314	\"O\315P\316\f\2066
	#*\207" [auto-mode-alist filename-regexp mode-alist x directory default-directory nil "\\`[^.].*\\(" vhdl-mode "\\|" 0 string-match "\\\\|$" "\\)" vhdl-directory-files full] 6 (#$ . 146840)])
#@114 Scan directory for all VHDL source files and generate menu.
The directory of the current source file is scanned.
(defalias 'vhdl-add-source-files-menu #[nil "\304\305!\210\306 \307 \310\211\310\n\203)\311\312\n@\313\n@D\311#	B\nA\211\204\314	\315\"\2036\316	B\317	B\315	B\320	!\210\321\310!\210\322\323\324	$\210,\304\325!\207" [found menu-list file-list newmap message "Scanning directory for source files ..." current-local-map vhdl-get-source-files nil t vector find-file vhdl-menu-split "Sources" "--" ["*Rescan*" vhdl-add-source-files-menu t] easy-menu-add (lambda (#1=#:def-tmp-var) (defvar vhdl-sources-menu #1# #2="VHDL source files menu")) easy-menu-do-define vhdl-sources-menu #2# ""] 6 (#$ . 147279) nil])
(byte-code "\300\301N\204\302\300\301\303\304!#\210\305\306!\204\302\306\307\310#\210\300\207" [vhdl-mode-hook variable-documentation put purecopy "Hook run when entering (quote (VHDL (vhdl-electric-mode / (vhdl-stutter-mode /)) (vhdl-electric-mode e) (vhdl-stutter-mode s))) mode.\nNo problems result if this variable is not bound.\n`add-hook' automatically binds it.  (This is true for all hook variables.)" boundp vhdl-mode-map definition-name vhdl-mode] 5)
(defvar vhdl-mode-map (make-sparse-keymap))
(byte-code "\300\301N\204\302\300\301\303\304!#\210\305\306!\204\302\306\307\310#\210\300\207" [vhdl-mode-map variable-documentation put purecopy "Keymap for `vhdl-mode'." boundp vhdl-mode-syntax-table definition-name vhdl-mode] 5)
(defvar vhdl-mode-syntax-table (make-syntax-table))
(byte-code "\300\301N\204\302\300\301\303\304!#\210\302\305\306\307#\207" [vhdl-mode-syntax-table variable-documentation put purecopy "Syntax table for `vhdl-mode'." vhdl-mode derived-mode-parent prog-mode] 5)
#@25672 Major mode for editing VHDL code.

Usage:
------

  TEMPLATE INSERTION (electrification):
    After typing a VHDL keyword and entering `SPC', you are prompted for
    arguments while a template is generated for that VHDL construct.  Typing
    `RET' or `C-g' at the first (mandatory) prompt aborts the current
    template generation.  Optional arguments are indicated by square
    brackets and removed if the queried string is left empty.  Prompts for
    mandatory arguments remain in the code if the queried string is left
    empty.  They can be queried again by `C-c C-t C-q'.  Enabled
    electrification is indicated by `/e' in the mode line.

      Typing `M-SPC' after a keyword inserts a space without calling the
    template generator.  Automatic template generation (i.e.
    electrification) can be disabled (enabled) by typing `C-c C-m C-e' or by
    setting option `vhdl-electric-mode' (see OPTIONS).

      Template generators can be invoked from the VHDL menu, by key
    bindings, by typing `C-c C-i C-c' and choosing a construct, or by typing
    the keyword (i.e. first word of menu entry not in parenthesis) and
    `SPC'.  The following abbreviations can also be used: arch, attr, cond,
    conf, comp, cons, func, inst, pack, sig, var.

      Template styles can be customized in customization group
    `vhdl-template' (see OPTIONS).


  HEADER INSERTION:
    A file header can be inserted by `C-c C-t C-h'.  A file footer
    (template at the end of the file) can be inserted by `C-c C-t C-f'.
    See customization group `vhdl-header'.


  STUTTERING:
    Double striking of some keys inserts cumbersome VHDL syntax elements.
    Stuttering can be disabled (enabled) by typing `C-c C-m C-s' or by
    option `vhdl-stutter-mode'.  Enabled stuttering is indicated by `/s' in
    the mode line.  The stuttering keys and their effects are:

      ;;   -->  " : "       [   -->  (        --    -->  comment
      ;;;  -->  " := "      [[  -->  [        --CR  -->  comment-out code
      ..   -->  " => "      ]   -->  )        ---   -->  horizontal line
      ,,   -->  " <= "      ]]  -->  ]        ----  -->  display comment
      ==   -->  " == "      ''  -->  \"


  WORD COMPLETION:
    Typing `TAB' after a (not completed) word looks for a VHDL keyword or a
    word in the buffer that starts alike, inserts it and adjusts case.
    Re-typing `TAB' toggles through alternative word completions.  This also
    works in the minibuffer (i.e. in template generator prompts).

      Typing `TAB' after `(' looks for and inserts complete parenthesized
    expressions (e.g. for array index ranges).  All keywords as well as
    standard types and subprograms of VHDL have predefined abbreviations
    (e.g. type "std" and `TAB' will toggle through all standard types
    beginning with "std").

      Typing `TAB' after a non-word character indents the line if at the
    beginning of a line (i.e. no preceding non-blank characters), and
    inserts a tabulator stop otherwise.  `M-TAB' always inserts a tabulator
    stop.


  COMMENTS:
        `--'       puts a single comment.
        `---'      draws a horizontal line for separating code segments.
        `----'     inserts a display comment, i.e. two horizontal lines
                   with a comment in between.
        `--CR'     comments out code on that line.  Re-hitting CR comments
                   out following lines.
        `C-c C-c'  comments out a region if not commented out,
                   uncomments a region if already commented out.  Option
                   `comment-style' defines where the comment characters
                   should be placed (beginning of line, indent, etc.).

      You are prompted for comments after object definitions (i.e. signals,
    variables, constants, ports) and after subprogram and process
    specifications if option `vhdl-prompt-for-comments' is non-nil.
    Comments are automatically inserted as additional labels (e.g. after
    begin statements) and as help comments if `vhdl-self-insert-comments' is
    non-nil.

      Inline comments (i.e. comments after a piece of code on the same line)
    are indented at least to `vhdl-inline-comment-column'.  Comments go at
    maximum to `vhdl-end-comment-column'.  `RET' after a space in a comment
    will open a new comment line.  Typing beyond `vhdl-end-comment-column'
    in a comment automatically opens a new comment line.  `M-q' re-fills
    multi-line comments.


  INDENTATION:
    `TAB' indents a line if at the beginning of the line.  The amount of
    indentation is specified by option `vhdl-basic-offset'.  `C-c C-i C-l'
    always indents the current line (is bound to `TAB' if option
    `vhdl-intelligent-tab' is nil).  If a region is active, `TAB' indents
    the entire region.

      Indentation can be done for a group of lines (`C-c C-i C-g'), a region
    (`M-C-\') or the entire buffer (menu).  Argument and port lists are
    indented normally (nil) or relative to the opening parenthesis (non-nil)
    according to option `vhdl-argument-list-indent'.

      If option `vhdl-indent-tabs-mode' is nil, spaces are used instead of
    tabs.  `M-x tabify' and `M-x untabify' allow to convert spaces to tabs
    and vice versa.

      Syntax-based indentation can be very slow in large files.  Option
    `vhdl-indent-syntax-based' allows to use faster but simpler indentation.

      Option `vhdl-indent-comment-like-next-code-line' controls whether
    comment lines are indented like the preceding or like the following code
    line.


  ALIGNMENT:
    The alignment functions align operators, keywords, and inline comments
    to beautify the code.  `C-c C-a C-a' aligns a group of consecutive lines
    separated by blank lines, `C-c C-a C-i' a block of lines with same
    indent.  `C-c C-a C-l' aligns all lines belonging to a list enclosed by
    a pair of parentheses (e.g. port clause/map, argument list), and `C-c
    C-a C-d' all lines within the declarative part of a design unit.  `C-c
    C-a M-a' aligns an entire region.  `C-c C-a C-c' aligns inline comments
    for a group of lines, and `C-c C-a M-c' for a region.

      If option `vhdl-align-groups' is non-nil, groups of code lines
    separated by special lines (see option `vhdl-align-group-separate') are
    aligned individually.  If option `vhdl-align-same-indent' is non-nil,
    blocks of lines with same indent are aligned separately.  Some templates
    are automatically aligned after generation if option `vhdl-auto-align'
    is non-nil.

      Alignment tries to align inline comments at
    `vhdl-inline-comment-column' and tries inline comment not to exceed
    `vhdl-end-comment-column'.

      `C-c C-x M-w' fixes up whitespace in a region.  That is, operator
    symbols are surrounded by one space, and multiple spaces are eliminated.


  CODE FILLING:
    Code filling allows to condense code (e.g. sensitivity lists or port
    maps) by removing comments and newlines and re-wrapping so that all
    lines are maximally filled (block filling).  `C-c C-f C-f' fills a list
    enclosed by parenthesis, `C-c C-f C-g' a group of lines separated by
    blank lines, `C-c C-f C-i' a block of lines with same indent, and
    `C-c C-f M-f' an entire region.


  CODE BEAUTIFICATION:
    `C-c M-b' and `C-c C-b' beautify the code of a region or of the entire
    buffer respectively.  This includes indentation, alignment, and case
    fixing.  Code beautification can also be run non-interactively using the
    command:

      emacs -batch -l ~/.emacs filename.vhd -f vhdl-beautify-buffer


  PORT TRANSLATION:
    Generic and port clauses from entity or component declarations can be
    copied (`C-c C-p C-w') and pasted as entity and component declarations,
    as component instantiations and corresponding internal constants and
    signals, as a generic map with constants as actual generics, and as
    internal signal initializations (menu).

      To include formals in component instantiations, see option
    `vhdl-association-list-with-formals'.  To include comments in pasting,
    see options `vhdl-include-...-comments'.

      A clause with several generic/port names on the same line can be
    flattened (`C-c C-p C-f') so that only one name per line exists.  The
    direction of ports can be reversed (`C-c C-p C-r'), i.e., inputs become
    outputs and vice versa, which can be useful in testbenches.  (This
    reversion is done on the internal data structure and is only reflected
    in subsequent paste operations.)

      Names for actual ports, instances, testbenches, and
    design-under-test instances can be derived from existing names according
    to options `vhdl-...-name'.  See customization group `vhdl-port'.


  SUBPROGRAM TRANSLATION:
    Similar functionality exists for copying/pasting the interface of
    subprograms (function/procedure).  A subprogram interface can be copied
    and then pasted as a subprogram declaration, body or call (uses
    association list with formals).


  TESTBENCH GENERATION:
    A copied port can also be pasted as a testbench.  The generated
    testbench includes an entity, an architecture, and an optional
    configuration.  The architecture contains the component declaration and
    instantiation of the DUT as well as internal constant and signal
    declarations.  Additional user-defined templates can be inserted.  The
    names used for entity/architecture/configuration/DUT as well as the file
    structure to be generated can be customized. See customization group
   `vhdl-testbench'.


  KEY BINDINGS:
    Key bindings (`C-c ...') exist for most commands (see in menu).


  VHDL MENU:
    All commands can be found in the VHDL menu including their key bindings.


  FILE BROWSER:
    The speedbar allows browsing of directories and file contents.  It can
    be accessed from the VHDL menu and is automatically opened if option
    `vhdl-speedbar-auto-open' is non-nil.

      In speedbar, open files and directories with `mouse-2' on the name and
    browse/rescan their contents with `mouse-2'/`S-mouse-2' on the `+'.


  DESIGN HIERARCHY BROWSER:
    The speedbar can also be used for browsing the hierarchy of design units
    contained in the source files of the current directory or the specified
    projects (see option `vhdl-project-alist').

      The speedbar can be switched between file, directory hierarchy and
    project hierarchy browsing mode in the speedbar menu or by typing `f',
    `h' or `H' in speedbar.

      In speedbar, open design units with `mouse-2' on the name and browse
    their hierarchy with `mouse-2' on the `+'.  Ports can directly be copied
    from entities and components (in packages).  Individual design units and
    complete designs can directly be compiled ("Make" menu entry).

      The hierarchy is automatically updated upon saving a modified source
    file when option `vhdl-speedbar-update-on-saving' is non-nil.  The
    hierarchy is only updated for projects that have been opened once in the
    speedbar.  The hierarchy is cached between Emacs sessions in a file (see
    options in group `vhdl-speedbar').

      Simple design consistency checks are done during scanning, such as
    multiple declarations of the same unit or missing primary units that are
    required by secondary units.


  STRUCTURAL COMPOSITION:
    Enables simple structural composition.  `C-c C-m C-n' creates a skeleton
    for a new component.  Subcomponents (i.e. component declaration and
    instantiation) can be automatically placed from a previously read port
    (`C-c C-m C-p') or directly from the hierarchy browser (`P').  Finally,
    all subcomponents can be automatically connected using internal signals
    and ports (`C-c C-m C-w') following these rules:
      - subcomponent actual ports with same name are considered to be
        connected by a signal (internal signal or port)
      - signals that are only inputs to subcomponents are considered as
        inputs to this component -> input port created
      - signals that are only outputs from subcomponents are considered as
        outputs from this component -> output port created
      - signals that are inputs to AND outputs from subcomponents are
        considered as internal connections -> internal signal created

      Purpose:  With appropriate naming conventions it is possible to
    create higher design levels with only a few mouse clicks or key
    strokes.  A new design level can be created by simply generating a new
    component, placing the required subcomponents from the hierarchy
    browser, and wiring everything automatically.

      Note: Automatic wiring only works reliably on templates of new
    components and component instantiations that were created by VHDL mode.

      Component declarations can be placed in a components package (option
    `vhdl-use-components-package') which can be automatically generated for
    an entire directory or project (`C-c C-m M-p').  The VHDL'93 direct
    component instantiation is also supported (option
    `vhdl-use-direct-instantiation').

      Configuration declarations can automatically be generated either from
    the menu (`C-c C-m C-f') (for the architecture the cursor is in) or from
    the speedbar menu (for the architecture under the cursor).  The
    configurations can optionally be hierarchical (i.e. include all
    component levels of a hierarchical design, option
    `vhdl-compose-configuration-hierarchical') or include subconfigurations
    (option `vhdl-compose-configuration-use-subconfiguration').  For
    subcomponents in hierarchical configurations, the most-recently-analyzed
    (mra) architecture is selected.  If another architecture is desired, it
    can be marked as most-recently-analyzed (speedbar menu) before
    generating the configuration.

      Note: Configurations of subcomponents (i.e. hierarchical configuration
    declarations) are currently not considered when displaying
    configurations in speedbar.

      See the options group `vhdl-compose' for all relevant user options.


  SOURCE FILE COMPILATION:
    The syntax of the current buffer can be analyzed by calling a VHDL
    compiler (menu, `C-c C-k').  The compiler to be used is specified by
    option `vhdl-compiler'.  The available compilers are listed in option
    `vhdl-compiler-alist' including all required compilation command,
    command options, compilation directory, and error message syntax
    information.  New compilers can be added.

      All the source files of an entire design can be compiled by the `make'
    command (menu, `C-c M-C-k') if an appropriate Makefile exists.


  MAKEFILE GENERATION:
    Makefiles can be generated automatically by an internal generation
    routine (`C-c M-k').  The library unit dependency information is
    obtained from the hierarchy browser.  Makefile generation can be
    customized for each compiler in option `vhdl-compiler-alist'.

      Makefile generation can also be run non-interactively using the
    command:

        emacs -batch -l ~/.emacs -l vhdl-mode
              [-compiler compilername] [-project projectname]
              -f vhdl-generate-makefile

      The Makefile's default target "all" compiles the entire design, the
    target "clean" removes it and the target "library" creates the
    library directory if not existent.  These target names can be customized
    by option `vhdl-makefile-default-targets'.  The Makefile also includes a
    target for each primary library unit which allows selective compilation
    of this unit, its secondary units and its subhierarchy (example:
    compilation of a design specified by a configuration).  User specific
    parts can be inserted into a Makefile with option
    `vhdl-makefile-generation-hook'.

    Limitations:
      - Only library units and dependencies within the current library are
        considered.  Makefiles for designs that span multiple libraries are
        not (yet) supported.
      - Only one-level configurations are supported (also hierarchical),
        but configurations that go down several levels are not.
      - The "others" keyword in configurations is not supported.


  PROJECTS:
    Projects can be defined in option `vhdl-project-alist' and a current
    project be selected using option `vhdl-project' (permanently) or from
    the menu or speedbar (temporarily).  For each project, title and
    description strings (for the file headers), source files/directories
    (for the hierarchy browser and Makefile generation), library name, and
    compiler-dependent options, exceptions and compilation directory can be
    specified.  Compilation settings overwrite the settings of option
    `vhdl-compiler-alist'.

      Project setups can be exported (i.e. written to a file) and imported.
    Imported setups are not automatically saved in `vhdl-project-alist' but
    can be saved afterwards in its customization buffer.  When starting
    Emacs with VHDL Mode (i.e. load a VHDL file or use "emacs -l
    vhdl-mode") in a directory with an existing project setup file, it is
    automatically loaded and its project activated if option
    `vhdl-project-auto-load' is non-nil.  Names/paths of the project setup
    files can be specified in option `vhdl-project-file-name'.  Multiple
    project setups can be automatically loaded from global directories.
    This is an alternative to specifying project setups with option
    `vhdl-project-alist'.


  SPECIAL MENUES:
    As an alternative to the speedbar, an index menu can be added (set
    option `vhdl-index-menu' to non-nil) or made accessible as a mouse menu
    (e.g. add "(global-set-key '[S-down-mouse-3] 'imenu)" to your start-up
    file) for browsing the file contents (is not populated if buffer is
    larger than `font-lock-maximum-size').  Also, a source file menu can be
    added (set option `vhdl-source-file-menu' to non-nil) for browsing the
    current directory for VHDL source files.


  VHDL STANDARDS:
    The VHDL standards to be used are specified in option `vhdl-standard'.
    Available standards are: VHDL'87/'93(02), VHDL-AMS, and Math Packages.


  KEYWORD CASE:
    Lower and upper case for keywords and standardized types, attributes,
    and enumeration values is supported.  If the option
    `vhdl-upper-case-keywords' is set to non-nil, keywords can be typed in
    lower case and are converted into upper case automatically (not for
    types, attributes, and enumeration values).  The case of keywords,
    types, attributes,and enumeration values can be fixed for an entire
    region (menu) or buffer (`C-c C-x C-c') according to the options
    `vhdl-upper-case-{keywords,types,attributes,enum-values}'.


  HIGHLIGHTING (fontification):
    Keywords and standardized types, attributes, enumeration values, and
    function names (controlled by option `vhdl-highlight-keywords'), as well
    as comments, strings, and template prompts are highlighted using
    different colors.  Unit, subprogram, signal, variable, constant,
    parameter and generic/port names in declarations as well as labels are
    highlighted if option `vhdl-highlight-names' is non-nil.

      Additional reserved words or words with a forbidden syntax (e.g. words
    that should be avoided) can be specified in option
    `vhdl-forbidden-words' or `vhdl-forbidden-syntax' and be highlighted in
    a warning color (option `vhdl-highlight-forbidden-words').  Verilog
    keywords are highlighted as forbidden words if option
    `vhdl-highlight-verilog-keywords' is non-nil.

      Words with special syntax can be highlighted by specifying their
    syntax and color in option `vhdl-special-syntax-alist' and by setting
    option `vhdl-highlight-special-words' to non-nil.  This allows to
    establish some naming conventions (e.g. to distinguish different kinds
    of signals or other objects by using name suffices) and to support them
    visually.

      Option `vhdl-highlight-case-sensitive' can be set to non-nil in order
    to support case-sensitive highlighting.  However, keywords are then only
    highlighted if written in lower case.

      Code between "translate_off" and "translate_on" pragmas is
    highlighted using a different background color if option
    `vhdl-highlight-translate-off' is non-nil.

      For documentation and customization of the used colors see
    customization group `vhdl-highlight-faces' (`M-x customize-group').  For
    highlighting of matching parenthesis, see customization group
    `paren-showing'.  Automatic buffer highlighting is turned on/off by
    option `global-font-lock-mode' (`font-lock-auto-fontify' in XEmacs).


  USER MODELS:
    VHDL models (templates) can be specified by the user and made accessible
    in the menu, through key bindings (`C-c C-m ...'), or by keyword
    electrification.  See option `vhdl-model-alist'.


  HIDE/SHOW:
    The code of blocks, processes, subprograms, component declarations and
    instantiations, generic/port clauses, and configuration declarations can
    be hidden using the `Hide/Show' menu or by pressing `S-mouse-2' within
    the code (see customization group `vhdl-menu').  XEmacs: limited
    functionality due to old `hideshow.el' package.


  CODE UPDATING:
    - Sensitivity List: `C-c C-u C-s' updates the sensitivity list of the
      current process, `C-c C-u M-s' of all processes in the current buffer.
      Limitations:
        - Only declared local signals (ports, signals declared in
          architecture and blocks) are automatically inserted.
        - Global signals declared in packages are not automatically inserted.
          Insert them once manually (will be kept afterwards).
        - Out parameters of procedures are considered to be read.
      Use option `vhdl-entity-file-name' to specify the entity file name
      (used to obtain the port names).
      Use option `vhdl-array-index-record-field-in-sensitivity-list' to
      specify whether to include array indices and record fields in
      sensitivity lists.


  CODE FIXING:
    `C-c C-x C-p' fixes the closing parenthesis of a generic/port clause
    (e.g. if the closing parenthesis is on the wrong line or is missing).


  PRINTING:
    PostScript printing with different faces (an optimized set of faces is
    used if `vhdl-print-customize-faces' is non-nil) or colors (if
    `ps-print-color-p' is non-nil) is possible using the standard Emacs
    PostScript printing commands.  Option `vhdl-print-two-column' defines
    appropriate default settings for nice landscape two-column printing.
    The paper format can be set by option `ps-paper-type'.  Do not forget to
    switch `ps-print-color-p' to nil for printing on black-and-white
    printers.


  OPTIONS:
    User options allow customization of VHDL Mode.  All options are
    accessible from the "Options" menu entry.  Simple options (switches
    and choices) can directly be changed, while for complex options a
    customization buffer is opened.  Changed options can be saved for future
    sessions using the "Save Options" menu entry.

      Options and their detailed descriptions can also be accessed by using
    the "Customize" menu entry or the command `M-x customize-option' (`M-x
    customize-group' for groups).  Some customizations only take effect
    after some action (read the NOTE in the option documentation).
    Customization can also be done globally (i.e. site-wide, read the
    INSTALL file).

      Not all options are described in this documentation, so go and see
    what other useful user options there are (`M-x vhdl-customize' or menu)!


  FILE EXTENSIONS:
    As default, files with extensions ".vhd" and ".vhdl" are
    automatically recognized as VHDL source files.  To add an extension
    ".xxx", add the following line to your Emacs start-up file (`.emacs'):

      (setq auto-mode-alist (cons '("\\.xxx\\'" . vhdl-mode) auto-mode-alist))


  HINTS:
    - To start Emacs with open VHDL hierarchy browser without having to load
      a VHDL file first, use the command:

        emacs -l vhdl-mode -f speedbar-frame-mode

    - Type `C-g C-g' to interrupt long operations or if Emacs hangs.

    - Some features only work on properly indented code.


  RELEASE NOTES:
    See also the release notes (menu) for added features in new releases.


Maintenance:
------------

To submit a bug report, enter `M-x vhdl-submit-bug-report' within VHDL Mode.
Add a description of the problem and include a reproducible test case.

Questions and enhancement requests can be sent to <reto@gnu.org>.

The `vhdl-mode-announce' mailing list informs about new VHDL Mode releases.
The `vhdl-mode-victims' mailing list informs about new VHDL Mode beta
releases.  You are kindly invited to participate in beta testing.  Subscribe
to above mailing lists by sending an email to <reto@gnu.org>.

VHDL Mode is officially distributed at
http://www.iis.ee.ethz.ch/~zimmi/emacs/vhdl-mode.html
where the latest version can be found.


Known problems:
---------------

- XEmacs: Incorrect start-up when automatically opening speedbar.
- XEmacs: Indentation in XEmacs 21.4 (and higher).
- Indentation incorrect for new 'postponed' VHDL keyword.
- Indentation incorrect for 'protected body' construct.


                                                The VHDL Mode Authors
                                            Reto Zimmermann and Rod Whitby

Key bindings:
-------------

\{vhdl-mode-map}

In addition to any hooks its parent mode `prog-mode' might have run,
this mode runs the hook `vhdl-mode-hook', as the final step
during initialization.
(defalias 'vhdl-mode #[nil "\306\300!\210\307\310 \210\311\312\310\313N\203\314\311\313\310\313N#\210\315!\204'\316\317 \"\210\320\f!\211\2036
\321 =\203<\322\f\323 \"\210)\324!\210\325\f!\210@A\306\326!\210\327\306\330!\210\306\331!\210\307\306\332!\210\307\306\333!\210\334\306\335!\210\336\306\337!\210\340B\203\207\306\341!\210\340!\306\342!\210C\"\306\343!\210D#\306\344!\210\345$\306\346!\210\347&\306\350!\210E(\306\351!\210\347)\352\353!\203\301\306\353!\210\354+\306\355!\210\356\347F?\357\360\257-\306\361!\210\3621B\204\370\306\363!\210\3643\306\365!\210\3475\306\366!\210\3076\306\367!\210\3077G\203
\306\370!\210\3478\306\371!\210\3479\372 \210H\203
\373 \210\374I!\210\375\347!\210\376\377\201LI$\210\201M \210\201N\201O!\210\201P \210\201Q \210\201R\201SJK\203Q
\340\202T
\201T#\210)\201U\201V!\207" [delay-mode-hooks major-mode mode-name vhdl-mode-map vhdl-mode-syntax-table parent make-local-variable t prog-mode vhdl-mode ("VHDL" (vhdl-electric-mode "/" (vhdl-stutter-mode "/")) (vhdl-electric-mode "e") (vhdl-stutter-mode "s")) mode-class put keymap-parent set-keymap-parent current-local-map char-table-parent standard-syntax-table set-char-table-parent syntax-table use-local-map set-syntax-table paragraph-start "\\s-*\\(--+\\s-*$\\|[^ -]\\|$\\)" paragraph-separate paragraph-ignore-fill-prefix parse-sexp-ignore-comments indent-line-function vhdl-indent-line comment-start "--" comment-end "" comment-padding comment-column end-comment-column comment-start-skip "--+\\s-*" comment-multi-line nil indent-tabs-mode hippie-expand-verbose boundp comment-indent-function vhdl-comment-indent font-lock-defaults (nil vhdl-font-lock-keywords) ((95 . "w")) beginning-of-line syntax-propertize-function #[(start end) "b\210`	W\205:\302\303	\304#\205:\305\224\204\306\224\203\305\224\203)\307\305\224\305\225\310\311$\210\306\224\203\307\306\224\306\225\310\312$\210\202\207" [start end re-search-forward "\\('\\).\\('\\)" t 1 2 put-text-property syntax-table (7 . 39) (7 . 39)] 5] font-lock-support-mode lazy-lock-mode lazy-lock-defer-contextually lazy-lock-defer-on-the-fly lazy-lock-defer-on-scrolling compilation-error-regexp-alist compilation-file-regexp-alist vhdl-index-menu-init vhdl-add-source-files-menu easy-menu-add (lambda (#1=#:def-tmp-var) (defvar vhdl-mode-menu #1# #2="Menu keymap for VHDL Mode.")) easy-menu-do-define vhdl-mode-menu vhdl-mode-abbrev-table local-abbrev-table vhdl-emacs-21 vhdl-inline-comment-column vhdl-end-comment-column vhdl-indent-tabs-mode vhdl-highlight-case-sensitive vhdl-compile-use-local-error-regexp vhdl-source-file-menu vhdl-mode-menu-list vhdl-version noninteractive #2# vhdl-hideshow-init run-hooks menu-bar-update-hook vhdl-ps-print-init vhdl-write-file-hooks-init message "VHDL Mode %s.%s" "  See menu for documentation and release notes." run-mode-hooks vhdl-mode-hook] 6 (#$ . 149032) nil])
#@49 Activate all customizations on local variables.
(defalias 'vhdl-activate-customizations #[nil "\306 \210\307!\210\310	!\210\n\f\311 \210\312 \210\313 \210\314\315!\207" [vhdl-mode-map vhdl-mode-syntax-table vhdl-inline-comment-column comment-column vhdl-end-comment-column end-comment-column vhdl-mode-map-init use-local-map set-syntax-table vhdl-write-file-hooks-init vhdl-update-mode-menu vhdl-hideshow-init run-hooks menu-bar-update-hook] 2 (#$ . 177654) nil])
#@40 Add/remove hooks when buffer is saved.
(defalias 'vhdl-write-file-hooks-init #[nil "\203\301\302\303\304\305$\210\202\306\302\303\305#\210\301\307\310\304\305$\207" [vhdl-modify-date-on-saving add-hook local-write-file-hooks vhdl-template-modify-noerror nil t remove-hook after-save-hook vhdl-add-modified-file] 5 (#$ . 178127)])
#@45 Process command line options for VHDL Mode.
(defalias 'vhdl-process-command-line-option #[(option) "\302\232\203\303	@!\210	A\211\207\304\232\205\305	@!\210	A\211\207" [option command-line-args-left "-compiler" vhdl-set-compiler "-project" vhdl-set-project] 2 (#$ . 178468)])
(byte-code "\301\302\"\301\207" [command-switch-alist append (("-compiler" . vhdl-process-command-line-option) ("-project" . vhdl-process-command-line-option))] 3)
#@27 List of VHDL'02 keywords.
(defconst vhdl-02-keywords '("abs" "access" "after" "alias" "all" "and" "architecture" "array" "assert" "attribute" "begin" "block" "body" "buffer" "bus" "case" "component" "configuration" "constant" "disconnect" "downto" "else" "elsif" "end" "entity" "exit" "file" "for" "function" "generate" "generic" "group" "guarded" "if" "impure" "in" "inertial" "inout" "is" "label" "library" "linkage" "literal" "loop" "map" "mod" "nand" "new" "next" "nor" "not" "null" "of" "on" "open" "or" "others" "out" "package" "port" "postponed" "procedure" "process" "protected" "pure" "range" "record" "register" "reject" "rem" "report" "return" "rol" "ror" "select" "severity" "shared" "signal" "sla" "sll" "sra" "srl" "subtype" "then" "to" "transport" "type" "unaffected" "units" "until" "use" "variable" "wait" "when" "while" "with" "xnor" "xor") (#$ . 178924))
#@28 List of VHDL-AMS keywords.
(defconst vhdl-ams-keywords '("across" "break" "limit" "nature" "noise" "procedural" "quantity" "reference" "spectrum" "subnature" "terminal" "through" "tolerance") (#$ . 179804))
#@70 List of Verilog keywords as candidate for additional reserved words.
(defconst vhdl-verilog-keywords '("`define" "`else" "`endif" "`ifdef" "`include" "`timescale" "`undef" "always" "and" "assign" "begin" "buf" "bufif0" "bufif1" "case" "casex" "casez" "cmos" "deassign" "default" "defparam" "disable" "edge" "else" "end" "endattribute" "endcase" "endfunction" "endmodule" "endprimitive" "endspecify" "endtable" "endtask" "event" "for" "force" "forever" "fork" "function" "highz0" "highz1" "if" "initial" "inout" "input" "integer" "join" "large" "macromodule" "makefile" "medium" "module" "nand" "negedge" "nmos" "nor" "not" "notif0" "notif1" "or" "output" "parameter" "pmos" "posedge" "primitive" "pull0" "pull1" "pulldown" "pullup" "rcmos" "real" "realtime" "reg" "release" "repeat" "rnmos" "rpmos" "rtran" "rtranif0" "rtranif1" "scalared" "signed" "small" "specify" "specparam" "strength" "strong0" "strong1" "supply" "supply0" "supply1" "table" "task" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1" "triand" "trior" "trireg" "vectored" "wait" "wand" "weak0" "weak1" "while" "wire" "wor" "xnor" "xor") (#$ . 180017))
#@37 List of VHDL'02 standardized types.
(defconst vhdl-02-types '("boolean" "bit" "bit_vector" "character" "severity_level" "integer" "real" "time" "natural" "positive" "string" "line" "text" "side" "unsigned" "signed" "delay_length" "file_open_kind" "file_open_status" "std_logic" "std_logic_vector" "std_ulogic" "std_ulogic_vector") (#$ . 181148))
#@38 List of VHDL-AMS standardized types.
(defconst vhdl-ams-types '("domain_type" "real_vector" "energy" "power" "periodicity" "real_across" "real_through" "unspecified" "unspecified_vector" "energy_vector" "power_vector" "periodicity_vector" "real_across_vector" "real_through_vector" "voltage" "current" "charge" "resistance" "conductance" "capacitance" "mmf" "electric_flux" "electric_flux_density" "electric_field_strength" "magnetic_flux" "magnetic_flux_density" "magnetic_field_strength" "inductance" "reluctance" "electrical" "electrical_vector" "magnetic" "magnetic_vector" "voltage_vector" "current_vector" "mmf_vector" "magnetic_flux_vector" "charge_vector" "resistance_vector" "conductance_vector" "capacitance_vector" "electric_flux_vector" "electric_flux_density_vector" "electric_field_strength_vector" "magnetic_flux_density_vector" "magnetic_field_strength_vector" "inductance_vector" "reluctance_vector" "ground" "displacement" "force" "velocity" "acceleration" "mass" "stiffness" "damping" "momentum" "angle" "torque" "angular_velocity" "angular_acceleration" "moment_inertia" "angular_momentum" "angular_stiffness" "angular_damping" "translational" "translational_vector" "translational_velocity" "translational_velocity_vector" "rotational" "rotational_vector" "rotational_velocity" "rotational_velocity_vector" "displacement_vector" "force_vector" "velocity_vector" "force_velocity_vector" "angle_vector" "torque_vector" "angular_velocity_vector" "torque_velocity_vector" "acceleration_vector" "mass_vector" "stiffness_vector" "damping_vector" "momentum_vector" "angular_acceleration_vector" "moment_inertia_vector" "angular_momentum_vector" "angular_stiffness_vector" "angular_damping_vector" "anchor" "translational_v_ref" "rotational_v_ref" "translational_v" "rotational_v" "illuminance" "luminous_flux" "luminous_intensity" "irradiance" "radiant" "radiant_vector" "luminous_intensity_vector" "luminous_flux_vector" "illuminance_vector" "irradiance_vector" "temperature" "heat_flow" "thermal_capacitance" "thermal_resistance" "thermal_conductance" "thermal" "thermal_vector" "temperature_vector" "heat_flow_vector" "thermal_capacitance_vector" "thermal_resistance_vector" "thermal_conductance_vector" "pressure" "vflow_rate" "mass_flow_rate" "volume" "density" "viscosity" "fresistance" "fconductance" "fcapacitance" "inertance" "cfresistance" "cfcapacitance" "cfinertance" "cfconductance" "fluidic" "fluidic_vector" "compressible_fluidic" "compressible_fluidic_vector" "pressure_vector" "vflow_rate_vector" "mass_flow_rate_vector" "volume_vector" "density_vector" "viscosity_vector" "fresistance_vector" "fconductance_vector" "fcapacitance_vector" "inertance_vector" "cfresistance_vector" "cfconductance_vector" "cfcapacitance_vector" "cfinertance_vector") (#$ . 181500))
#@43 List of Math Packages standardized types.
(defconst vhdl-math-types '("complex" "complex_polar" "positive_real" "principal_value") (#$ . 184299))
#@42 List of VHDL'02 standardized attributes.
(defconst vhdl-02-attributes '("base" "left" "right" "high" "low" "pos" "val" "succ" "pred" "leftof" "rightof" "range" "reverse_range" "length" "delayed" "stable" "quiet" "transaction" "event" "active" "last_event" "last_active" "last_value" "driving" "driving_value" "ascending" "value" "image" "simple_name" "instance_name" "path_name" "foreign") (#$ . 184451))
#@43 List of VHDL-AMS standardized attributes.
(defconst vhdl-ams-attributes '("across" "through" "reference" "contribution" "tolerance" "dot" "integ" "delayed" "above" "zoh" "ltf" "ztf" "ramp" "slew") (#$ . 184862))
#@50 List of VHDL'02 standardized enumeration values.
(defconst vhdl-02-enum-values '("true" "false" "note" "warning" "error" "failure" "read_mode" "write_mode" "append_mode" "open_ok" "status_error" "name_error" "mode_error" "fs" "ps" "ns" "us" "ms" "sec" "min" "hr" "right" "left") (#$ . 185080))
#@51 List of VHDL-AMS standardized enumeration values.
(defconst vhdl-ams-enum-values '("quiescent_domain" "time_domain" "frequency_domain" "eps0" "mu0" "ground" "mecvf_gnd" "mecpf_gnd" "rot_gnd" "fld_gnd") (#$ . 185380))
#@42 List of VHDL-AMS standardized constants.
(defconst vhdl-ams-constants '("phys_q" "phys_eps0" "phys_mu0" "phys_k" "phys_gravity" "phys_ctok" "phys_c" "phys_h" "phys_h_over_2_pi" "yocto" "zepto" "atto" "femto" "pico" "nano" "micro" "milli" "centi" "deci" "deka" "hecto" "kilo" "mega" "giga" "tera" "peta" "exa" "zetta" "yotta" "deca" "phys_eps_si" "phys_eps_sio2" "phys_e_si" "phys_e_sio2" "phys_e_poly" "phys_nu_si" "phys_nu_poly" "phys_rho_poly" "phys_rho_sio2" "ambient_temperature" "ambient_pressure" "ambient_illuminance") (#$ . 185603))
#@47 List of Math Packages standardized constants.
(defconst vhdl-math-constants '("math_1_over_e" "math_1_over_pi" "math_1_over_sqrt_2" "math_2_pi" "math_3_pi_over_2" "math_cbase_1" "math_cbase_j" "math_czero" "math_deg_to_rad" "math_e" "math_log10_of_e" "math_log2_of_e" "math_log_of_10" "math_log_of_2" "math_pi" "math_pi_over_2" "math_pi_over_3" "math_pi_over_4" "math_rad_to_deg" "math_sqrt_2" "math_sqrt_pi") (#$ . 186150))
#@41 List of VHDL'02 standardized functions.
(defconst vhdl-02-functions '("now" "resolved" "rising_edge" "falling_edge" "read" "readline" "hread" "oread" "write" "writeline" "hwrite" "owrite" "endfile" "resize" "is_X" "std_match" "shift_left" "shift_right" "rotate_left" "rotate_right" "to_unsigned" "to_signed" "to_integer" "to_stdLogicVector" "to_stdULogic" "to_stdULogicVector" "to_bit" "to_bitVector" "to_X01" "to_X01Z" "to_UX01" "to_01" "conv_unsigned" "conv_signed" "conv_integer" "conv_std_logic_vector" "shl" "shr" "ext" "sxt" "deallocate") (#$ . 186581))
#@42 List of VHDL-AMS standardized functions.
(defconst vhdl-ams-functions '("frequency") (#$ . 187147))
#@47 List of Math Packages standardized functions.
(defconst vhdl-math-functions '("arccos" "arccosh" "arcsin" "arcsinh" "arctan" "arctanh" "arg" "cbrt" "ceil" "cmplx" "complex_to_polar" "conj" "cos" "cosh" "exp" "floor" "get_principal_value" "log" "log10" "log2" "polar_to_complex" "realmax" "realmin" "round" "sign" "sin" "sinh" "sqrt" "tan" "tanh" "trunc" "uniform") (#$ . 187253))
#@54 List of VHDL'02 standardized packages and libraries.
(defconst vhdl-02-packages '("std_logic_1164" "numeric_std" "numeric_bit" "standard" "textio" "std_logic_arith" "std_logic_signed" "std_logic_unsigned" "std_logic_misc" "std_logic_textio" "ieee" "std" "work") (#$ . 187639))
#@55 List of VHDL-AMS standardized packages and libraries.
(defconst vhdl-ams-packages '("fundamental_constants" "material_constants" "energy_systems" "electrical_systems" "mechanical_systems" "radiant_systems" "thermal_systems" "fluidic_systems") (#$ . 187922))
#@60 List of Math Packages standardized packages and libraries.
(defconst vhdl-math-packages '("math_real" "math_complex") (#$ . 188186))
#@24 List of VHDL keywords.
(defvar vhdl-keywords nil (#$ . 188325))
#@34 List of VHDL standardized types.
(defvar vhdl-types nil (#$ . 188395))
#@39 List of VHDL standardized attributes.
(defvar vhdl-attributes nil (#$ . 188472))
#@47 List of VHDL standardized enumeration values.
(defvar vhdl-enum-values nil (#$ . 188559))
#@38 List of VHDL standardized constants.
(defvar vhdl-constants nil (#$ . 188655))
#@38 List of VHDL standardized functions.
(defvar vhdl-functions nil (#$ . 188740))
#@51 List of VHDL standardized packages and libraries.
(defvar vhdl-packages nil (#$ . 188825))
#@36 List of additional reserved words.
(defvar vhdl-reserved-words nil (#$ . 188922))
#@27 Regexp for VHDL keywords.
(defvar vhdl-keywords-regexp nil (#$ . 189010))
#@37 Regexp for VHDL standardized types.
(defvar vhdl-types-regexp nil (#$ . 189090))
#@42 Regexp for VHDL standardized attributes.
(defvar vhdl-attributes-regexp nil (#$ . 189177))
#@50 Regexp for VHDL standardized enumeration values.
(defvar vhdl-enum-values-regexp nil (#$ . 189274))
#@41 Regexp for VHDL standardized constants.
(defvar vhdl-constants-regexp nil (#$ . 189380))
#@41 Regexp for VHDL standardized functions.
(defvar vhdl-functions-regexp nil (#$ . 189475))
#@54 Regexp for VHDL standardized packages and libraries.
(defvar vhdl-packages-regexp nil (#$ . 189570))
#@39 Regexp for additional reserved words.
(defvar vhdl-reserved-words-regexp nil (#$ . 189677))
#@41 Regexp for compiler directive keywords.
(defvar vhdl-directive-keywords-regexp nil (#$ . 189775))
#@49 Upcase all elements in LIST based on CONDITION.
(defalias 'vhdl-upcase-list #[(condition list) "\203	\211\203\n\211@\226\240\210\nA\211\204\n)	\207" [condition list tmp-list] 3 (#$ . 189879)])
#@28 Initialize reserved words.
(defalias 'vhdl-words-init #[nil "\306\205	\307\n\310\311!\205\"\"\306\205
\307\310\311!\205#\310\312!\205+#\"\306\2056\307\310\311!\205A\"\"\306\205L\307\310\311!\205W\"\" \306\205b!\307\310\311!\205k\"\310\312!\205s#\313#\"$\307%\310\311!\205\203&\310\312!\205\213'#(\307)\310\311!\205\231*\310\312!\205\241+#,\307-\205\254./\205\2630\314#1\315\316\f!\317Q2\315\316!\317Q3\315\316!\317Q4\315\316 !\317Q5\315\316$!\317Q6\315\316(!\317Q7\315\316,!\317Q8\3159\320\232?\205
9\321P\3161!\317R:\315\322\323;\321#\317Q<\324 \207" [vhdl-highlight-case-sensitive vhdl-upper-case-keywords vhdl-02-keywords vhdl-ams-keywords vhdl-keywords vhdl-upper-case-types vhdl-upcase-list append vhdl-standard-p ams math (#1="") (#1#) "\\<\\(" regexp-opt "\\)\\>" #1# "\\|" mapconcat regexp-quote vhdl-abbrev-list-init vhdl-02-types vhdl-ams-types vhdl-math-types vhdl-types vhdl-upper-case-attributes vhdl-02-attributes vhdl-ams-attributes vhdl-attributes vhdl-upper-case-enum-values vhdl-02-enum-values vhdl-ams-enum-values vhdl-enum-values vhdl-upper-case-constants vhdl-ams-constants vhdl-math-constants vhdl-constants vhdl-02-functions vhdl-ams-functions vhdl-math-functions vhdl-functions vhdl-02-packages vhdl-ams-packages vhdl-math-packages vhdl-packages vhdl-highlight-forbidden-words vhdl-forbidden-words vhdl-highlight-verilog-keywords vhdl-verilog-keywords vhdl-reserved-words vhdl-keywords-regexp vhdl-types-regexp vhdl-attributes-regexp vhdl-enum-values-regexp vhdl-constants-regexp vhdl-functions-regexp vhdl-packages-regexp vhdl-forbidden-syntax vhdl-reserved-words-regexp vhdl-directive-keywords vhdl-directive-keywords-regexp] 7 (#$ . 190086)])
#@36 Predefined abbreviations for VHDL.
(defvar vhdl-abbrev-list nil (#$ . 191852))
(defalias 'vhdl-abbrev-list-init #[nil "\306C	\nC\fC
C	\nC\307C\f\307C
&\211\207" [vhdl-upper-case-keywords vhdl-keywords vhdl-upper-case-types vhdl-types vhdl-upper-case-attributes vhdl-attributes append nil vhdl-upper-case-enum-values vhdl-enum-values vhdl-upper-case-constants vhdl-constants vhdl-functions vhdl-packages vhdl-abbrev-list] 15])
(vhdl-words-init)
#@210 Regexp describing a VHDL symbol.
We cannot use just `word' syntax class since `_' cannot be in word
class.  Putting underscore in word class breaks forward word movement
behavior that users are familiar with.
(defconst vhdl-symbol-key "\\(\\w\\|\\s_\\)+" (#$ . 192316))
#@48 Regexp describing a case statement header key.
(defconst vhdl-case-header-key "case[( 	\n
\f][^;=>]+[) 	\n
\f]is" (#$ . 192592))
#@33 Regexp describing a VHDL label.
(defconst vhdl-label-key (concat "\\(" vhdl-symbol-key "\\s-*:\\)[^=]") (#$ . 192727))
#@431 Return the value of point at certain commonly referenced POSITIONs.
POSITION can be one of the following symbols:

bol  -- beginning of line
eol  -- end of line
bod  -- beginning of defun
boi  -- back to indentation
eoi  -- last whitespace on line
ionl -- indentation of next line
iopl -- indentation of previous line
bonl -- beginning of next line
bopl -- beginning of previous line

This function does not modify point or mark.
(defalias 'vhdl-point '(macro . #[(position) "\242\302=\203\211AA)\203\303\304\"\210A@\305\306\307\310=\203&\311\202z\312=\2030\313\202z\314=\203:\315\202z\316=\203D\317\202z\320=\203N\321\202z\322=\203X\323\202z\324=\203b\325\202z\326=\203l\327\202z\330=\203v\331\202z\303\332\"\333\334#BB\207" [position x quote error "ERROR:  Bad buffer position requested: %s" let ((here (point))) append bol ((beginning-of-line)) eol ((end-of-line)) bod ((save-match-data (vhdl-beginning-of-defun))) boi ((back-to-indentation)) eoi ((end-of-line) (skip-chars-backward " 	")) bonl ((forward-line 1)) bopl ((forward-line -1)) iopl ((forward-line -1) (back-to-indentation)) ionl ((forward-line 1) (back-to-indentation)) "ERROR:  Unknown buffer position requested: %s" ((prog1 (point) (goto-char here))) nil] 7 (#$ . 192853)]))
#@55 Safely execute BODY, return nil if an error occurred.
(defalias 'vhdl-safe '(macro . #[(&rest body) "\301\302\303B\304BBB\207" [body condition-case nil progn ((error nil))] 4 (#$ . 194139)]))
#@116 A simple macro to append the syntax in SYMBOL to the syntax list.
Try to increase performance by using this macro.
(defalias 'vhdl-add-syntax '(macro . #[(symbol &optional relpos) "\302\303\304\211	E\305BBE\207" [symbol relpos setq vhdl-syntactic-context cons (vhdl-syntactic-context)] 6 (#$ . 194339)]))
#@98 A simple macro to return check the syntax list.
Try to increase performance by using this macro.
(defalias 'vhdl-has-syntax '(macro . #[(symbol) "\301\302BB\207" [symbol assoc (vhdl-syntactic-context)] 3 (#$ . 194651)]))
#@80 Read new offset value for LANGELEM from minibuffer.
Return a valid value only.
(defalias 'vhdl-read-offset #[(langelem) "\306\307	\236\243\"\310\311\312\211\211\f\204w\313
\"\211\314\230\203(\315\202r\316\230\2032\317\202r\320\230\203<\321\202r\322\230\203F\323\202r\324\325\"\203S\326!\202r\327\330!\211!\203a\n\202r\331\n!\203k\n\202r\332 \210\312\211\203\f.\207" [langelem vhdl-offsets-alist interned input offset prompt format "%s" "Offset must be int, func, var, or one of +, -, ++, --: " "Offset: " nil read-string "+" + "-" - "++" ++ "--" -- string-match "^-?[0-9]+$" string-to-number fboundp intern boundp ding errmsg oldoff] 7 (#$ . 194879)])
#@274 Change the value of a syntactic element symbol in `vhdl-offsets-alist'.
SYMBOL is the syntactic element symbol to change and OFFSET is the new
offset for that syntactic element.  Optional ADD-P says to add SYMBOL to
`vhdl-offsets-alist' if it doesn't already appear there.
(defalias 'vhdl-set-offset #[(symbol offset &optional add-p) "\305=\204.\306=\204.\307=\204.\310=\204.\250\204.\311!\204.\312!\204.\313\314\"\210	\n\236\211\203=\241\210\202O\f\203J	B\nB\202O\313\315	\"\210)\316 \207" [offset symbol vhdl-offsets-alist entry add-p + - ++ -- fboundp boundp error "ERROR:  Offset must be int, func, var, or one of +, -, ++, --: %s" "ERROR:  %s is not a valid syntactic symbol" vhdl-keep-region-active] 4 (#$ . 195579) (let* ((langelem (intern (completing-read (concat "Syntactic symbol to change" (if current-prefix-arg " or add" "") ": ") (mapcar #'(lambda (langelem) (cons (format "%s" (car langelem)) nil)) vhdl-offsets-alist) nil (not current-prefix-arg) (let* ((syntax (vhdl-get-syntactic-context)) (len (length syntax)) (ic (format "%s" (car (nth (1- len) syntax))))) ic)))) (offset (vhdl-read-offset langelem))) (list langelem offset current-prefix-arg))])
#@418 Set `vhdl-mode' variables to use one of several different indentation styles.
STYLE is a string representing the desired style and optional LOCAL is
a flag which, if non-nil, means to make the style variables being
changed buffer local, instead of the default, which is to set the
global variables.  Interactively, the flag comes from the prefix
argument.  The styles are chosen from the `vhdl-style-alist' variable.
(defalias 'vhdl-set-style #[(style &optional local) "\303	\"A\211\204\304\305\"\210\306\307\n\"\210)\310 \207" [style vhdl-style-alist vars assoc error "ERROR:  Invalid VHDL indentation style `%s'" mapc #[(varentry) "@A\211\305=\204\203\306\n!\202\n	L\2020\203&\306\n!\202'\n\307\f!L\210\310\311	\"*\207" [varentry val var local vhdl-offsets-alist-default vhdl-offsets-alist make-local-variable copy-alist mapcar #[(langentry) "@A\303\n	\"*\207" [langentry offset langelem vhdl-set-offset] 3]] 4] vhdl-keep-region-active] 4 (#$ . 196778) (list (completing-read "Use which VHDL indentation style? " vhdl-style-alist nil t) current-prefix-arg)])
#@270 Get offset from LANGELEM which is a cons cell of the form:
(SYMBOL . RELPOS).  The symbol is matched against
vhdl-offsets-alist and the offset found there is either returned,
or added to the indentation at RELPOS.  If RELPOS is nil, then
the offset is simply returned.
(defalias 'vhdl-get-offset #[(langelem) "@A	\236\211\243\f\204%\203\306\307	\"\210\202v\310\211\202v
\311=\2031\202v
\312=\203>[\202v
\313=\203L\314_\202v
\315=\203[[\314_\202v
\247\204m\316
!\203m
!\202v
\247\204v\317
!\n\203\224\n`\320 \210`b\210)W\203\224\212\nb\210i)\202\225\310
\\,\207" [langelem symbol relpos vhdl-offsets-alist match offset error "ERROR:  Don't know how to indent a %s" 0 + - ++ 2 -- fboundp eval beginning-of-line vhdl-strict-syntax-p vhdl-basic-offset here] 4 (#$ . 197870)])
#@33 Check if point is in a comment.
(defalias 'vhdl-in-comment-p #[nil "\300 \301=\207" [vhdl-in-literal comment] 2 (#$ . 198698)])
#@32 Check if point is in a string.
(defalias 'vhdl-in-string-p #[nil "\300 \301=\207" [vhdl-in-literal string] 2 (#$ . 198832)])
#@37 Check if point is in a quote ('x').
(defalias 'vhdl-in-quote-p #[nil "`eV\203`TdW\203`Sf\300U\203`Tf\300U\2067`SeV\2057`dW\2057`SSf\300U\2057`f\300U\207" [39] 2 (#$ . 198963)])
#@42 Determine if point is in a VHDL literal.
(defalias 'vhdl-in-literal #[nil "\212\302`\303 \210`b\210)`\"\304	8\203\305\202-\306	8\203#\307\202-\310 \203,\311\202-\312*\207" [here state parse-partial-sexp beginning-of-line 3 string 4 comment vhdl-beginning-of-macro pound nil] 3 (#$ . 199156)])
#@69 Determine if point is inside extended identifier (delimited by '').
(defalias 'vhdl-in-extended-identifier-p #[nil "\302 \303\216\212\304\305`\306 \210`	b\210)\307#)\205(\212\310\305`\311\210`	b\210)\307#)*\207" [save-match-data-internal here match-data ((byte-code "\301\302\"\207" [save-match-data-internal set-match-data evaporate] 3)) re-search-backward "\\\\" beginning-of-line t re-search-forward nil] 4 (#$ . 199465)])
#@109 Skip all comments (including whitespace).  Skip backwards if DIRECTION is
negative, skip forward otherwise.
(defalias 'vhdl-forward-comment #[(&optional direction) "\203*\302W\203*\303\304x\210\305\306`\307 \210`	b\210)\310#\205?\311\224b\210\303\304x\210\202\303\304w\210\312\313!\205?\302\225b\210\303\304w\210\202.\207" [direction here 0 " 	\n
\f" nil re-search-backward "^[^\"-]*\\(\\(-?\"[^\"]*\"\\|-[^\"-]\\)[^\"-]*\\)*\\(--\\)" beginning-of-line t 3 looking-at "--.*"] 4 (#$ . 199904) "p"])
(defalias 'vhdl-forward-comment 'forward-comment)
#@64 Move point to the first non-whitespace character on this line.
(defalias 'vhdl-back-to-indentation #[nil "\301\302!\210\303\304`\305\210`b\210)\"\207" [here beginning-of-line 1 skip-syntax-forward " " nil] 4 (#$ . 200468) nil])
#@42 Determine if point is in a VHDL literal.
(defalias 'vhdl-win-il #[(&optional lim) "\212`\305\211\206`\306 \307\216\310 \210*`b\210)\211b\210`W\203\205\311\312\313#\2052\314\224\314\225{\211\204;\305\202\201\n\315\230\203N\305\210`X\205\201\316\202\201\n\317\230\203g\214`}\210\311\320\313#)?\205\201\321\202\201\n\322\230\203\200\214`}\210\311\323\313#)?\205\201\321\202\201\305\202	-\207" [here state match lim save-match-data-internal nil match-data ((byte-code "\301\302\"\207" [save-match-data-internal set-match-data evaporate] 3)) vhdl-beginning-of-defun re-search-forward "--\\|[\"']" move 0 "--" comment "\"" "\\([^\\]\\|^\\)\\(\\\\\\\\\\)*\"" string "'" "\\([^\\]\\|^\\)\\(\\\\\\\\\\)?'"] 5 (#$ . 200705)])
(byte-code "\301\302\"\203\303\304M\210\301\207" [emacs-version string-match "Win-Emacs" vhdl-in-literal vhdl-win-il] 3)
#@39 Forward skip of syntactic whitespace.
(defalias 'vhdl-forward-syntactic-ws #[(&optional lim) "dd`U\204D`\303	!\210\304f\305=\203`\306 \210`b\210)`U\203`\304\210`b\210)Sf\307=\203>\310y\311U\204&\304\210\202\n\205L`\n^b*\207" [here hugenum lim vhdl-forward-comment nil 35 back-to-indentation 92 1 0] 2 (#$ . 201587)])
#@50 Forward skip syntactic whitespace for Win-Emacs.
(defalias 'vhdl-win-fsws #[(&optional lim) "\206d\302	?\205#\303w\210\304\305!\203\302\210\202\306\211\202	*\207" [lim stop nil " 	\n
\f" looking-at "--" t] 3 (#$ . 201930)])
(byte-code "\301\302\"\203\303\304M\210\301\207" [emacs-version string-match "Win-Emacs" vhdl-forward-syntactic-ws vhdl-win-fsws] 3)
#@74 Go to the beginning of a cpp macro definition (nicked from `cc-engine').
(defalias 'vhdl-beginning-of-macro #[(&optional lim) "`\301 \210`SSf\302=\203\303y\210\202\304 \210`X\203(\305f\306=\203(\307\202,b\210\305)\207" [here beginning-of-line 92 -1 back-to-indentation nil 35 t] 2 (#$ . 202310)])
#@42 Backward skip over syntactic whitespace.
(defalias 'vhdl-backward-syntactic-ws #[(&optional lim) "ed[`U\204`\303	!\210\304 \210\202\n\205`\n]b*\207" [here hugenum lim vhdl-forward-comment vhdl-beginning-of-macro] 2 (#$ . 202623)])
#@51 Backward skip syntactic whitespace for Win-Emacs.
(defalias 'vhdl-win-bsws #[(&optional lim) "\206`\304 \305\216\306 \210*`	b\210)\307?\205T\310x\210\311 \312=\203N\313x\210\314x\210g\315U\203=`Tf\315U\204`X\204\313x\210\314x\210\202/\316\211\202*\207" [lim here save-match-data-internal stop match-data ((byte-code "\301\302\"\207" [save-match-data-internal set-match-data evaporate] 3)) vhdl-beginning-of-defun nil " 	\n
\f" vhdl-in-literal comment "^-" "-" 45 t] 3 (#$ . 202870)])
(byte-code "\301\302\"\203\303\304M\210\301\207" [emacs-version string-match "Win-Emacs" vhdl-backward-syntactic-ws vhdl-win-bsws] 3)
#@90 If the keyword at POINT is at boi, then return (current-column) at
that point, else nil.
(defalias 'vhdl-first-word #[(point) "\212b\205``\302 \210`	b\210)=\205i)\207" [point here back-to-indentation] 3 (#$ . 203523)])
#@90 If the keyword at POINT is at eoi, then return (current-column) at
that point, else nil.
(defalias 'vhdl-last-word #[(point) "\212b\205%\212\302 \210``\303\210\304\303x\210`	b\210)=\206 \305\306!)\205%i)\207" [point here forward-sexp nil " 	" looking-at "\\s-*\\(--\\)?"] 3 (#$ . 203754)])
(defconst vhdl-libunit-re "\\b\\(architecture\\|configuration\\|entity\\|package\\)\\b[^_]")
(defalias 'vhdl-libunit-p #[nil "\212\300 \210\301\302w\210\303\304!)?\205&\212\305 \210\303\306!?\205%\300 \210\307 \210g\310U?)\207" [forward-sexp " 	\n
\f" nil looking-at "is\\b[^_]" backward-sexp "use\\b[^_]" vhdl-forward-syntactic-ws 58] 2])
(defconst vhdl-defun-re "\\b\\(architecture\\|block\\|configuration\\|entity\\|package\\|process\\|procedural\\|procedure\\|function\\)\\b[^_]")
(defalias 'vhdl-defun-p #[nil "\212\300\301!\203\212\302 \210\300\303!)?\202\304)\207" [looking-at "block\\|process\\|procedural" backward-sexp "end\\s-+\\w" t] 2])
#@169 If the word at the current position corresponds to a "defun"
keyword, then return a string that can be used to find the
corresponding "begin" keyword, else return nil.
(defalias 'vhdl-corresponding-defun #[nil "\212\301!\205\302 \205\301\303!\203\304\224\304\225{\202\305)\207" [vhdl-defun-re looking-at vhdl-defun-p "block\\|process\\|procedural" 0 "is"] 2 (#$ . 204713)])
#@85 A regular expression for searching forward that matches all known
"begin" keywords.
(defconst vhdl-begin-fwd-re "\\b\\(is\\|begin\\|block\\|component\\|generate\\|then\\|else\\|loop\\|process\\|procedural\\(\\s-+body\\)?\\|units\\|use\\|record\\|protected\\(\\s-+body\\)?\\|for\\)\\b\\([^_]\\|\\'\\)" (#$ . 205102))
#@86 A regular expression for searching backward that matches all known
"begin" keywords.
(defconst vhdl-begin-bwd-re "\\b\\(is\\|begin\\|block\\|component\\|generate\\|then\\|else\\|loop\\|process\\|procedural\\(\\s-+body\\)?\\|units\\|use\\|record\\|protected\\(\\s-+body\\)?\\|for\\)\\b[^_]" (#$ . 205424))
#@265 Return t if we are looking at a real "begin" keyword.
Assumes that the caller will make sure that we are looking at
vhdl-begin-fwd-re, and are not inside a literal, and that we are not in
the middle of an identifier that just happens to contain a "begin"
keyword.
(defalias 'vhdl-begin-p #[(&optional lim) "\303\304!\203A\212\305 \210\306\204/\307\310	\311#\203/h\312U\204#\313 \203)\314u\210\202\f\315\211\203)g\316U?\205;\303\317!?)\203A\315\207\303\320!\203I\315\207\303\321!\203e\212\322\323	\311#\210g\316=\206_`	=)\203e\315\207\303\324!\203x\212\305 \210\303\325!)\204x\315\207\303\326!\203\227\212\305 \210\303\325!)\204\227\212\327	!\210h\330U)\204\227\315\207\303\331!\205\261\212\305 \210\303\325!)?\205\261\332\333\n\"\205\261\315\207" [foundp lim vhdl-syntactic-context looking-at "i" backward-sexp nil re-search-backward ";\\|\\b\\(architecture\\|case\\|configuration\\|entity\\|package\\|procedure\\|return\\|is\\|begin\\|process\\|procedural\\|block\\)\\b[^_]" move 95 vhdl-in-literal -1 t 59 "is\\|begin\\|process\\|procedural\\|block" "be\\|t\\|use" "e" vhdl-re-search-backward ";\\|\\bwhen\\b[^_]" "block\\|generate\\|loop\\|process\\|procedural\\|protected\\(\\s-+body\\)?\\|units\\|record" "end\\s-+\\w" "c" vhdl-backward-syntactic-ws 58 "f" assoc configuration] 5 (#$ . 205736)])
(defalias 'vhdl-corresponding-mid #[(&optional lim) "\300\301!\203\302\207\300\303!\203\304\207\305\207" [looking-at "is\\|block\\|generate\\|process\\|procedural" "begin" "then\\|use" "<else>" "end"] 2])
#@449 If the word at the current position corresponds to a "begin"
keyword, then return a vector containing enough information to find
the corresponding "end" keyword, else return nil.  The keyword to
search forward for is aref 0.  The column in which the keyword must
appear is aref 1 or nil if any column is suitable.
Assumes that the caller will make sure that we are not in the middle
of an identifier that just happens to contain a "begin" keyword.
(defalias 'vhdl-corresponding-end #[(&optional lim) "\212\302!\205\303\302\303!\203\212\304 \210\302\305!)\205\303h\306U?\205\303\307 ?\205\303\310	!\205\303\302\311!\203P\312\313\314`!\205L\315`!\206L\212\316	!\210\317	!\210\315`!)\"\202\303\302\320!\203u\312\313\314`!\205q\315`!\206q\212\316	!\210\317	!\210\315`!)\"\202\303\302\321!\203\202\312\313\322\"\202\303\302\323!\203\241\312\313\315`!\206\235\212\316	!\210\317	!\210\315`!)\"\202\303\302\324!\205\303\312\325\314`!\205\302\315`!\206\302\212\316	!\210\317	!\210\315`!)\")\207" [vhdl-begin-fwd-re lim looking-at "\\<use\\>" back-to-indentation "\\(\\w+\\s-*:\\s-*\\)?\\<\\(case\\|elsif\\|if\\)\\>" 95 vhdl-in-literal vhdl-begin-p "[igl]" vector "end" vhdl-last-word vhdl-first-word vhdl-beginning-of-statement-1 vhdl-backward-skip-label "be\\|[ef]" "component\\|units\\|protected\\(\\s-+body\\)?\\|record" nil "bl\\|p" "t\\|use" "elsif\\|else\\|end\\s-+\\(if\\|use\\)"] 4 (#$ . 207278)])
(defconst vhdl-end-fwd-re "\\b\\(end\\|else\\|elsif\\)\\b\\([^_]\\|\\'\\)")
(defconst vhdl-end-bwd-re "\\b\\(end\\|else\\|elsif\\)\\b[^_]")
#@260 Return t if we are looking at a real "end" keyword.
Assumes that the caller will make sure that we are looking at
vhdl-end-fwd-re, and are not inside a literal, and that we are not in
the middle of an identifier that just happens to contain an "end"
keyword.
(defalias 'vhdl-end-p #[(&optional lim) "\301\302!?\206\212\303\304\305#\210g\306=\206`=\206\307 )\207" [lim looking-at "else" re-search-backward ";\\|\\bwhen\\b[^_]" move 59 vhdl-in-literal] 4 (#$ . 208846)])
#@626 If the word at the current position corresponds to an "end"
keyword, then return a vector containing enough information to find
the corresponding "begin" keyword, else return nil.  The keyword to
search backward for is aref 0.  The column in which the keyword must
appear is aref 1 or nil if any column is suitable.  The supplementary
keyword to search forward for is aref 2 or nil if this is not
required.  If aref 3 is t, then the "begin" keyword may be found in
the middle of a statement.
Assumes that the caller will make sure that we are not in the middle
of an identifier that just happens to contain an "end" keyword.
(defalias 'vhdl-corresponding-begin #[(&optional lim) "\212\303\304	!\205\307\305 ?\205\307\306\n!\205\307\304\307!\203&\310\311\312`!\313\303$\202\307`\314 \210\315\303w\210\304\316!\203@\310\317\312!\320\303$\202\307\304\321!\203U\310\322\224\322\225{\312!\303\211$\202\307\304\323!\203j\310\322\224\322\225{\312!\303\324$\202\307\304\325!\203{\310\326\312!\303\211$\202\307\304\327!\203\214\310\330\312!\331\303$\202\307\304\332!\203\235\310\333\312!\334\303$\202\307\304\335!\203\256\310\336\312!\337\303$\202\307\304\340!\203\277\310\341\312!\303\211$\202\307\310\342\312!\343\303$*\207" [pos vhdl-end-fwd-re lim nil looking-at vhdl-in-literal vhdl-end-p "el" vector "if\\|elsif" vhdl-first-word "then\\|use" forward-sexp " 	\n
\f" "if\\b[^_]" "else\\|elsif\\|if" "else\\|then\\|use" "component\\b[^_]" 1 "\\(units\\|record\\|protected\\(\\s-+body\\)?\\)\\b[^_]" t "\\(block\\|process\\|procedural\\)\\b[^_]" "begin" "case\\b[^_]" "case" "is" "generate\\b[^_]" "generate\\|for\\|if" "generate" "loop\\b[^_]" "loop\\|while\\|for" "loop" "for\\b[^_]" "for" "begin\\|architecture\\|configuration\\|entity\\|package\\|procedure\\|function" (("begin") ("architecture" . "is") ("configuration" . "is") ("entity" . "is") ("package" . "is") ("procedure" . "is") ("function" . "is"))] 5 (#$ . 209330)])
(defconst vhdl-leader-re "\\b\\(block\\|component\\|process\\|procedural\\|for\\)\\b[^_]")
(defalias 'vhdl-end-of-leader #[nil "\212\300\301!\203.\212\302 \210\303\304w\210g\305U)\203\302\306!\210\202 \302 \210\300\307!\203*\310\225b\210`\202i\300\311!\203F\302\306!\210\300\307!\203B\310\225b\210`\202i\300\312!\203h\302\306!\210\303\304w\210\300\313!\203d\302 \210\303\304w\210\202T`\202i\304)\207" [looking-at "block\\|process\\|procedural" forward-sexp " 	\n
\f" nil 40 2 "[ 	\n
\f]*is" 0 "component" "for" "[,:(]"] 2])
(defconst vhdl-trailer-re "\\b\\(is\\|then\\|generate\\|loop\\|record\\|protected\\(\\s-+body\\)?\\|use\\)\\b[^_]")
#@89 A regular expression for searching forward that matches all known
"statement" keywords.
(defconst vhdl-statement-fwd-re "\\b\\(if\\|for\\|while\\|loop\\)\\b\\([^_]\\|\\'\\)" (#$ . 211945))
#@90 A regular expression for searching backward that matches all known
"statement" keywords.
(defconst vhdl-statement-bwd-re "\\b\\(if\\|for\\|while\\|loop\\)\\b[^_]" (#$ . 212140))
#@277 Return t if we are looking at a real "statement" keyword.
Assumes that the caller will make sure that we are looking at
vhdl-statement-fwd-re, and are not inside a literal, and that we are not
in the middle of an identifier that just happens to contain a
"statement" keyword.
(defalias 'vhdl-statement-p #[(&optional lim) "\300\301!\203#\212\302\303!\210\304\305w\210\300\306!)\203#\212\307 \210\300\310!)\204#\311\207\300\312!\2036\212\307 \210\300\310!)\2046\311\207\300\313!\205=\311\207" [looking-at "f" forward-sexp 2 " 	\n
\f" nil "in\\b[^_]" backward-sexp "end\\s-+\\w" t "i" "w"] 2 (#$ . 212325)])
#@53 Regexp describing a case statement alternative key.
(defconst vhdl-case-alternative-re "when[( 	\n
\f][^;=>]+=>" (#$ . 212943))
#@272 Return t if we are looking at a real case alternative.
Assumes that the caller will make sure that we are looking at
vhdl-case-alternative-re, and are not inside a literal, and that
we are not in the middle of an identifier that just happens to
contain a "when" keyword.
(defalias 'vhdl-case-alternative-p #[(&optional lim) "\212\302\204&\303\304	\305#\203&h\306U\204\307 \203 \310u\210\202\311\211\203g\312=\206/`	=*\207" [foundp lim nil re-search-backward ";\\|<=" move 95 vhdl-in-literal -1 t 59] 5 (#$ . 213078)])
(defconst vhdl-b-t-b-re (concat vhdl-begin-bwd-re "\\|" vhdl-end-bwd-re))
#@57 Move backward to the previous "begin" or "end" keyword.
(defalias 'vhdl-backward-to-block #[(&optional lim) "\305\204`\306	\n\307#\203`h\310U\204\311 \203\312u\210\202\313!\203H\313\314!\2036\212\315 \210\313\316!)\203Hh\310U\204H\317\n!\203H\320\211\202\313\f!\203h\310U\204\321\n!\203\322\211\203)\207" [foundp vhdl-b-t-b-re lim vhdl-begin-fwd-re vhdl-end-fwd-re nil re-search-backward move 95 vhdl-in-literal -1 looking-at "\\<use\\>" back-to-indentation "\\(\\w+\\s-*:\\s-*\\)?\\<\\(case\\|elsif\\|if\\)\\>" vhdl-begin-p begin vhdl-end-p end] 5 (#$ . 213689)])
#@88 Move forward across one balanced expression (sexp).
With COUNT, do it that many times.
(defalias 'vhdl-forward-sexp #[(&optional count lim) "\206\306\307\310\211\212\311V\203\336\312\310w\210\313\f!\2038h\314U\2048\315 \2048\316
!\2038\313\317!\2048\320\321!\210\322
!\211\203\324\323\n\311H\324Q\n\306H`\310\210`b\210)\310\211\211 \204\306\325 \310\307#\203\306\306\225\211\203\306\311\224b\203\306\203\224\326 U\204\224`V\204\242h\314U\204\242\315 \211\203\265\327=\203\257\310\210\202d\310u\210\202d\313\317!\204\277b\210\307\211\203i\204\317\320\330!\210.\202\327\331 \210S\211\202`)	b\210,\310\207" [count target end-vec case-fold-search vhdl-end-fwd-re lim 1 t nil 0 " 	\n
\f" looking-at 95 vhdl-in-literal vhdl-end-p "else" error "ERROR:  Containing expression ends prematurely in vhdl-forward-sexp" vhdl-corresponding-end "\\b\\(" "\\)\\b\\([^_]\\|\\'\\)" re-search-forward current-indentation comment "ERROR:  Unbalanced keywords in vhdl-forward-sexp" forward-sexp here placeholder literal foundp eol column end-re] 7 (#$ . 214289) "p"])
#@133 Move backward across one balanced expression (sexp).
With COUNT, do it that many times.  LIM bounds any required backward
searches.
(defalias 'vhdl-backward-sexp #[(&optional count lim) "\206\306\307\310\211\212\311V\203i
\312\313!\203$h\314U\204$\315 \203S\316 \210\312\f!\203S\312\317!\203>\212\320 \210\312\321!)\203Sh\314U\204S\315 \204S\322
!\203S\323\324!\210\325
!\211\203b
h\314U\204b
\326\n\311H\327Q\n\306H\n\330H`\310\211\211\211!\"#$%&'(#\204W
\331(
\307#\203W
\306\224\306\225{\211!\203W
'\203\264\332 'U\204\264&\203\277i'U\203\277h\314U\204\277\315 \203\305\333u\210\202\202\n\334H\211(\203P
(<\203\351\335!(\"\211(\203P
(A\211(\203P
\326(\327Q\211(\203\202\212`$#\204C
\336(%\307#\203C
\306\224b\203C
h\314U\204
\315 \211\"\203<
\"\337=\2036
`)\310\210`)b\210)%^b\210\202\370\310u\210\202\370`\211#\203\375#)\203\202#b\210\202\202\307\211#\203\207#\204`
\323\340!\210.S\211\202`)	b\210,\310\207" [count target begin-vec case-fold-search vhdl-begin-fwd-re lim 1 t nil 0 looking-at "else\\b\\([^_]\\|\\'\\)" 95 vhdl-in-literal backward-sexp "\\<use\\>" back-to-indentation "\\(\\w+\\s-*:\\s-*\\)?\\<\\(case\\|elsif\\|if\\)\\>" vhdl-begin-p error "ERROR:  Containing expression ends prematurely in vhdl-backward-sexp" vhdl-corresponding-begin "\\b\\(" "\\)\\b[^_]" 3 re-search-backward current-indentation -1 2 assoc re-search-forward comment "ERROR:  Unbalanced keywords in vhdl-backward-sexp" keyword literal foundp last-forward last-backward internal-p column begin-re here] 9 (#$ . 215419) "p"])
#@83 Move backward out of one level of blocks.
With argument, do this that many times.
(defalias 'vhdl-backward-up-list #[(&optional count limit) "\206\304\305\212\306V\203$\307\n!\203\310\311!\210\312!\210S\211\202\n`)	b*\207" [count target vhdl-defun-re limit 1 nil 0 looking-at error "ERROR:  Unbalanced blocks" vhdl-backward-to-block] 3 (#$ . 217017) "p"])
#@42 Move forward to the end of a VHDL defun.
(defalias 'vhdl-end-of-defun #[(&optional count) "\301\302 \210\303\304!\204\305\306!\210\307 )\207" [case-fold-search t vhdl-beginning-of-defun looking-at "block\\|process\\|procedural" re-search-forward "\\bis\\b" vhdl-forward-sexp] 2 (#$ . 217393) nil])
#@54 Put mark at end of this "defun", point at beginning.
(defalias 'vhdl-mark-defun #[nil "\301\302 \210\303 \210\302 \210\304\305!\204\306\307!\210\310 \210\311 )\207" [case-fold-search t push-mark vhdl-beginning-of-defun looking-at "block\\|process\\|procedural" re-search-forward "\\bis\\b" vhdl-forward-sexp exchange-point-and-mark] 2 (#$ . 217700) nil])
#@485 Move backward to the beginning of a VHDL library unit.
Returns the location of the corresponding begin keyword, unless search
stops due to beginning or end of buffer.
Note that if point is between the "libunit" keyword and the
corresponding "begin" keyword, then that libunit will not be
recognized, and the search will continue backwards.  If point is
at the "begin" keyword, then the defun will be recognized.  The
returned point is at the first character of the "libunit" keyword.
(defalias 'vhdl-beginning-of-libunit #[nil "`\212\306v\210`T)\307\211\211\n\204\310
\307\311#\203h\312U\204,\313 \204,\314 \2042\315u\210\202`\n\204y\316\317\320#\203y\321\224\211\203yh\312U\204T\313 \211\203s	\322=\203m`\307\210`b\210)^b\210\2024\307u\210\2024\211\2038\fb\210\202\n-\207" [placeholder literal foundp last-backward last-forward vhdl-libunit-re 1 nil re-search-backward move 95 vhdl-in-literal vhdl-libunit-p -1 re-search-forward "\\bis\\b[^_]" t 0 comment here] 6 (#$ . 218065)])
#@199 Move backward to the beginning of a VHDL defun.
With argument, do it that many times.
Returns the location of the corresponding begin keyword, unless search
stops due to beginning or end of buffer.
(defalias 'vhdl-beginning-of-defun #[(&optional count) "\206\306\307`\310\211\311V\203\241\310\nb\210\212\306v\210`T)\310\211	\204\231\312\310\313#\203\231h\314U\204<\315 \203B\316u\210\202$\317 \211\203$`	\204\223\320
\307#\203\223h\314U\204l\321 \322\216\315 \211*\203\214\f\323=\203\206`\310\210`b\210)^b\210\202K\310u\210\202K\311\224\211\203O\nb\210\202$+S\211\202
\324 \210	,\207" [count foundp last-forward case-fold-search literal begin-string 1 t nil 0 re-search-backward move 95 vhdl-in-literal -1 vhdl-corresponding-defun search-forward match-data ((byte-code "\301\302\"\207" [save-match-data-internal set-match-data evaporate] 3)) comment vhdl-keep-region-active last-backward vhdl-defun-re save-match-data-internal here] 5 (#$ . 219090) "p"])
#@501 Go to the beginning of the innermost VHDL statement.
With prefix arg, go back N - 1 statements.  If already at the
beginning of a statement then go to the beginning of the preceding
one.  If within a string or comment, or next to a comment (only
whitespace between), move by sentences instead of statements.

When called from a program, this function takes 3 optional args: the
prefix arg, a buffer position limit which is the farthest back to
search, and an argument indicating an interactive call.
(defalias 'vhdl-beginning-of-statement #[(&optional count lim interactive) "\206\306\307	\206e`\310\212	b\210\311`\310\211$)
\203?\312\n8\2047\313\n8\2047\314\315P!\203?\316[!\210\202P\317V\203P\320	!\210S\211\202@`	]b\210-\321 \207" [count lim state here case-fold-search interactive 1 t nil parse-partial-sexp 3 4 looking-at "[ 	]*" forward-sentence 0 vhdl-beginning-of-statement-1 vhdl-keep-region-active comment-start-skip] 6 (#$ . 220101) "p\np"])
(defconst vhdl-e-o-s-re (concat ";\\|" vhdl-begin-fwd-re "\\|" vhdl-statement-fwd-re))
#@29 Very simple implementation.
(defalias 'vhdl-end-of-statement #[nil "\301!\207" [vhdl-e-o-s-re re-search-forward] 2 (#$ . 221172) nil])
(defconst vhdl-b-o-s-re (concat ";[^_]\\|([^_]\\|)[^_]\\|\\bwhen\\b[^_]\\|" vhdl-begin-bwd-re "\\|" vhdl-statement-bwd-re))
#@107 Move to the start of the current statement, or the previous
statement if already at the beginning of one.
(defalias 'vhdl-beginning-of-statement-1 #[(&optional lim) "\206e``\306\306\307\310\217\204 \311\312!\210\306u\210\313!\210\314	?\2053
o?\2053
\306u\210\315\f\316#\2053
h\317U\204@\320 \203F\321u\210\202 g\322=\203Y\306u\210\313!\210\314\211\202!g\323=\203z\306u\210`\324 \210`W\203 \nb\210\313!\210\314\211\202!g\325=\203\222\326 \204\222\306u\210\313!\210\314\211\202!\327
!\203\345\327\330!\203\251\212\331 \210\327\332!)\203\345h\317U\204\345\333\306!\203\345\327 !\203\323\212`\334 b\210\313!\210`W\203\317`)\202\334\312v\210\313!\210`\nb\210\314\211\202!\327!!\203\376h\317U\204\376\335\306!\203\376\314\211\202!\327\"!\203-
\336!\203-
\212`\327\"!\210\337\225b\210\313!\210`W\203#
`)\nb\210\314\211\202!\321u\210\202 ,\207" [lim donep pos here vhdl-b-o-s-re vhdl-begin-fwd-re nil (byte-code "\300 \210\301\207" [backward-sexp t] 1) ((error)) backward-up-list 1 vhdl-forward-syntactic-ws t re-search-backward move 95 vhdl-in-literal -1 40 41 backward-sexp 59 vhdl-in-quote-p looking-at "\\<use\\>" back-to-indentation "\\(\\w+\\s-*:\\s-*\\)?\\<\\(case\\|elsif\\|if\\)\\>" vhdl-begin-p vhdl-end-of-leader vhdl-statement-p vhdl-case-alternative-p 0 vhdl-leader-re vhdl-statement-fwd-re vhdl-case-alternative-re] 5 (#$ . 221439)])
#@123 If there is an enclosing library unit at BOD, with its "begin"
keyword at PLACEHOLDER, then return the library unit type.
(defalias 'vhdl-get-library-unit #[(bod placeholder) "`\303 \210`b\210)\212	b\210\304\305\306\217\210`X)\205[\212\nb\210\307\310!\203)\311\202Z\307\312!\2033\313\202Z\307\314!\203=\315\202Z\307\316!\205Z\212\nb\210\317 \210\320!\210\307\321!\203X\322\202Y\323)))\207" [here placeholder bod beginning-of-line nil (vhdl-forward-sexp 1 bod) ((error)) looking-at "e" entity "a" architecture "c" configuration "p" forward-sexp vhdl-forward-syntactic-ws "body\\b[^_]" package-body package] 3 (#$ . 222849)])
#@130 Finds and records all the closest opens.
LIM is the furthest back we need to search (it should be the
previous libunit keyword).
(defalias 'vhdl-get-block-state #[(&optional lim) "`\206e\306\211\211\211\211\211\211\211\211\212\214`}\210\306\307\310\217)\211\2031	`V\203\234\f\204\234\311!\211\312=\203u`\313!\306\314\315\217\211\203jX\203j
\2041\2021\316\2021\317=\2031\320 \210`\306\211\321\322\217\206\220\323 \210`
\2041\2021)	\203\263\f\203\253\f	W\203\263	\306\211\306\324\f
\n$.\207" [lim containing-paren containing-mid containing-begin containing-sexp preceding-sexp nil (byte-code "\300`\301\302#\207" [scan-lists -1 1] 4) ((error)) vhdl-backward-to-block begin vhdl-corresponding-mid (byte-code "\212\301\302\"\210`)\207" [lim vhdl-forward-sexp 1] 3) ((error)) t end forward-sexp (byte-code "\301\302\"\210`\207" [lim vhdl-backward-sexp 1] 3) ((error)) backward-sexp vector sexp-end sexp-mid sexp-start keyword here] 12 (#$ . 223495)])
(defconst vhdl-s-c-a-re (concat vhdl-case-alternative-re "\\|" vhdl-case-header-key))
#@145 Skip forward over case/when bodies, with optional maximal
limit.  If no next case alternative is found, nil is returned and
point is not moved.
(defalias 'vhdl-skip-case-alternative #[(&optional lim) "\206d`\306\211`W\203R\n\204R\307\f\310#\203\f\311 \312\216\313 *\204\f\314\224U\204\f\314\224b\210\315\316!\203K\307\317\320#\203K\321 \210\322 \210\202\f\320\211\202\f	\204Yb\210	,\207" [lim foundp donep here vhdl-s-c-a-re save-match-data-internal nil re-search-forward move match-data ((byte-code "\301\302\"\207" [save-match-data-internal set-match-data evaporate] 3)) vhdl-in-literal 0 looking-at "case" "\\bis[^_]" t backward-sexp vhdl-forward-sexp] 5 (#$ . 224616)])
#@122 Skip backward over a label, with optional maximal
limit.  If label is not found, nil is returned and point
is not moved.
(defalias 'vhdl-backward-skip-label #[(&optional lim) "\206e\303\212\304!\210h\305=\205\306 \210`\307\n!)\205!	b*\207" [lim placeholder vhdl-label-key nil vhdl-backward-syntactic-ws 58 backward-sexp looking-at] 2 (#$ . 225323)])
#@121 Skip forward over a label, with optional maximal
limit.  If label is not found, nil is returned and point
is not moved.
(defalias 'vhdl-forward-skip-label #[(&optional lim) "\206d\302	!\205\303\225b\210\304!)\207" [lim vhdl-label-key looking-at 0 vhdl-forward-syntactic-ws] 2 (#$ . 225690)])
#@67 Guess the syntactic description of the current line of VHDL code.
(defalias 'vhdl-get-syntactic-context #[nil "\212\214\306 \210`\307\310\211\310\211\310\21189\310\211:;\310\211<=\310\211>?\310\211@A\310B\212\311 ?`@)?\203V\312@?\"\211A\203VA@BBBB\313@!\211\203q\n\314H\n\315H\n\316H8\n\317H9\f\203\223\212\fb\210\320C!\203\204\321 :`D\306 \210`Db\210*\202\224e@b\210\322\310w\210\323 g<?\205\302\320E!\205\302\320\324!\203\300\212\325 \210\320\326!)\205\302\327 =?\205\322\320F!\205\322\330 >\331@!\210h;b\210\322\310w\210\332>\203\377`D\333y\210`Db\210)BBBB\202&\f\204\217
\212
\204
\334@!\210\202)

b\210``D\325 \210`Db\210)U\204)
\334@!\210o\2031
\335!\210`?)=\203F
\336?BBBB\202&>\203W
\337?BBBB\202&\331@!\210o\204k
h\340U\203w
\341 \204w
\342?BBBB\202&\334@!\210o\203\204
\335!\210\343`BBBB\202&8\204E\331\f!\210<\344=\203\270
\fb\210\345`D\325 \210`Db\210)BBBB\202&;\346=\203\330
\fb\210\347`D\325 \210`Db\210)BBBB\202&\212\fTb\210\322\310w\210\320\350!)\204'\212\334\f!\210\351\310x\210h\340U\203\341 \204\334\f!\210\351\310x\210\202\361
`\fX)\203'\fb\210\352`D\325 \210`Db\210)BBBB\202&\334\f!\210\335!\210\353`D\325 \210`Db\210)BBBB\202&=\203|\3209!\203|\fb\210\320G!\203b\354 \210\334\310!\210\355`D\325 \210`Db\210)!\210\336`BBBB\202&>\203\254\fb\210\320G!\203\222\354 \210\334\310!\210\355`D\325 \210`Db\210)!\210\337`BBBB\202&;\340U\204G=\203\307\320G!\204G\212\355\f!)\204G\320H!\203\323\356 \204G\212\334\f!\210\335!\210`\211?)V\203G?\fU\204G\212?b\210\320I!?\206\376\314\225V)\203G?J\212?b\210\357!\210`\211J)V\203-\212Jb\210J\325 \210`)=\203-J?)\343?BBBB=\203&\336\310BBBB\202&\320I!\203{\360\f!\203{\fb\210\320G!\203e\354 \210\334\310!\210\361`D\325 \210`Db\210)BBBB\202&:\203\207:b\210\202\215\fb\210\354 \210\335!\210`?\310K\320I!\203\272`K\362!\204\241\320I!\210\314\225b\210\335!\210`?\202\227K\203\321`U\203\321\363KBBBB\202%`W\203\360\342?BBBB=\203%\336\310BBBB\202%\fb\210\320G!\203
\354 \210\334\310!\210\355`D\325 \210`Db\210)!\210\364`BBBB=\203%\336\310BBBB)b\210\322\310w\210\320\350!\203;\365\310BBBB\366=\203I\367\310BBBBB.\207" [indent-point case-fold-search vec literal containing-sexp preceding-sexp beginning-of-line t nil vhdl-beginning-of-libunit vhdl-get-library-unit vhdl-get-block-state 0 1 2 3 looking-at vhdl-end-of-leader " 	" vhdl-in-literal "\\<use\\>" back-to-indentation "\\(\\w+\\s-*:\\s-*\\)?\\<\\(case\\|elsif\\|if\\)\\>" vhdl-begin-p vhdl-end-p vhdl-backward-syntactic-ws (string comment) -1 vhdl-beginning-of-statement-1 vhdl-forward-syntactic-ws block-open block-close 59 vhdl-in-quote-p statement statement-cont 41 arglist-close 40 arglist-intro "--" " 	(" arglist-cont-nonempty arglist-cont forward-sexp vhdl-backward-skip-label vhdl-statement-p vhdl-forward-skip-label vhdl-case-alternative-p case-alternative vhdl-skip-case-alternative statement-case-intro statement-block-intro comment pound cpp-macro containing-begin containing-mid containing-leader char-before-ip char-after-ip begin-after-ip end-after-ip placeholder lim library-unit vhdl-syntactic-context vhdl-leader-re here vhdl-begin-fwd-re vhdl-end-fwd-re vhdl-trailer-re vhdl-statement-fwd-re vhdl-case-alternative-re new incase-p] 4 (#$ . 225995)])
#@118 Lineup the current arglist line with the arglist appearing just
after the containing paren which starts the arglist.
(defalias 'vhdl-lineup-arglist #[(langelem) "\212\212@\305>\203 \306 \210\307\310!\210\311`\312\210`	b\210)w\210\202$Ab\210`)\212Ab\210i)\212\306 \210\313\314!)\203M\315\225b\210\316 \210\312u\210\317 \210iZ\202x\nb\210l\204u`\312\210`	b\210)\312u\210\311\312w\210`\317 \210`\fW\203t	b\210*iZ+\207" [langelem here containing-sexp cs-curcol eol (arglist-intro arglist-cont-nonempty) beginning-of-line backward-up-list 1 " 	" nil looking-at "[ 	]*)" 0 backward-sexp vhdl-forward-syntactic-ws] 3 (#$ . 229425)])
#@60 Lineup an arglist-intro line to just after the open paren.
(defalias 'vhdl-lineup-arglist-intro #[(langelem) "\212\212Ab\210i)\212\304 \210\305\306!\210\307`\310\210`	b\210)w\210i)\311\n\312#+\207" [langelem here ce-curcol cs-curcol beginning-of-line backward-up-list 1 " 	" nil - -1] 4 (#$ . 230076)])
#@133 Support old behavior for comment indentation.  We look at
vhdl-comment-only-line-offset to decide how to indent comment
only-lines.
(defalias 'vhdl-lineup-comment #[(langelem) "\212\302 \210iY\203\303 \202'n\204	\242\206'	\202'	\243\206'	\242\206'\304)\207" [comment-column vhdl-comment-only-line-offset back-to-indentation vhdl-comment-indent -1000] 2 (#$ . 230392)])
#@55 Line up statement-cont after the assignment operator.
(defalias 'vhdl-lineup-statement-cont #[(langelem) "\212A\212`\306 \210`\nb\210)b\210\307\310`\311\210`\nb\210)\312#\205.``\306 \210`\nb\210)Z)	b\210i\311
\204\210``\311\210`\nb\210)W\203\210\307\313`\311\210`\nb\210)\314#\210\315 \203d\311u\210\2027h\316U\203`\311\210`\nb\210)\317`\320\211#^b\210\2027\321\322!?\211\203;
\204\221\202\243\204\236\311u\210\323\311w\210\324\325i\f#-\207" [langelem relpos here assignp curcol foundp back-to-indentation re-search-forward "\\(<\\|:\\|=\\)=" nil t "\\(<\\|:\\|=\\)=\\|(" move vhdl-in-literal 40 scan-lists 1 looking-at "\\s-*$" " 	" 0 - vhdl-basic-offset] 6 (#$ . 230777)])
#@66 Array variable for progress information: 0 begin, 1 end, 2 time.
(defvar vhdl-progress-info nil (#$ . 231491))
#@30 Update progress information.
(defalias 'vhdl-update-progress-info #[(string pos) "\205F	?\205F\n\306 A@\307HZW\205F\310H\311HZ\211\311U\203.\312\f\313P\314\"\210\202>\312\f\315P
\311HZ\316_\245\314#\210)\307\306 A@I\207" [vhdl-progress-info noninteractive vhdl-progress-interval delta string pos current-time 2 1 0 message "... (100%s)" "%" "... (%2d%s)" 100] 6 (#$ . 231608)])
#@289 If preceding character is part of a word or a paren then hippie-expand,
else if right of non whitespace on line then insert tab,
else if last command was a tab or return then dedent one step or if a comment
toggle between normal indent and inline comment indent,
else indent `correctly'.
(defalias 'vhdl-electric-tab #[(&optional prefix-arg) "\306\307 \310\211\211\311
!\210\312\313!\203?\313 \314\n@\nA\"\211\203?\n@\315\316!>\2038	B\317\315\310#\210\nA\211\204#\320\216\321 \203Q\322\323 \324 \310#\210\202\377hz\325U\203v(?\310\326\327!\203g\206h\330)\331*!\210+\202\377h\332U\204\202h\333U\203\222(?\310)\334*!\210*\202\377i\335 V\203\237\336 \210\202\377\337\340!\203\335+\341=\204\263+\342=\203\335\335 \343U\203\303\344j\210\345 \210\202\377\335 ,W\203\325,j\210\345 \210\202\377\346 `|\210\202\377\335 -Y\203\374+\341=\204\363+\342=\203\374\347-\310\"\210\202\377\345 \210\341\211..\207" [overlay overlay-intangible-list overlay-all-list current-syntax-table case-fold-search vhdl-mode-ext-syntax-table t syntax-table nil set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) use-region-p vhdl-indent-region region-beginning region-end 119 boundp hippie-expand-only-buffers (vhdl-mode) vhdl-expand-abbrev 40 41 vhdl-expand-paren current-indentation insert-tab looking-at "--" vhdl-electric-tab vhdl-electric-return 0 1 indent-according-to-mode line-beginning-position backward-delete-char-untabify vhdl-word-completion-case-sensitive case-replace prefix-arg last-command comment-column vhdl-basic-offset this-command] 6 (#$ . 232006) "*P"])
#@97 newline-and-indent or indent-new-comment-line if in comment and preceding
character is a space.
(defalias 'vhdl-electric-return #[nil "h\300U\203\301 \203\302 \207h\303Y\203#h\304X\203#\301 \204#\305\306!\210\307 \207" [32 vhdl-in-comment-p indent-new-comment-line 97 122 vhdl-fix-case-word -1 newline-and-indent] 2 (#$ . 233859) nil])
#@82 Indent the current line as VHDL code.  Returns the amount of
indentation change.
(defalias 'vhdl-indent-line #[nil "\205\306 d`Z\307	\203_	\211@@)\310=\203,\311	@!
Y\203,\311	@!\202l\203K\212	\211@@)\310=\203J\312\313\314!\210\306 \211\2023)\203U\310\307B	B\315\316\317\311	\"\"\202l\212\313 \210\320\321\307\312#\210\322 )\211 \322 Z!\"\203\200\323\324	 #\210\212\313 \210\325\326!)#\327!!\203\226#\203\277`$\313 \210`$b\210)`$\330 \210`$b\210)|\210\313 \210#\203\273\331c\210 j\210)``$\330 \210`$b\210)W\203\327\330 \210\202\344d\nZ`V\203\344d\nZb\210\332\333!\210\334\335\336 \"\210!-\207" [vhdl-indent-syntax-based syntax pos is-comment x comment-column vhdl-get-syntactic-context nil comment vhdl-get-offset t beginning-of-line 2 apply + mapcar re-search-backward "^[^\n]" current-indentation message "syntax: %s, indent= %d" looking-at "\\s-*\f" zerop back-to-indentation "\f" run-hooks vhdl-special-indent-hook vhdl-update-progress-info "Indenting" vhdl-current-line vhdl-indent-comment-like-next-code-line indent shift-amt vhdl-echo-syntactic-information-p has-formfeed here] 6 (#$ . 234208) nil])
#@73 Indent region as VHDL code.
Adds progress reporting to `indent-region'.
(defalias 'vhdl-indent-region #[(beg end &optional column) "\203\305\306e	\"\306e\n\"\307#\310	\n\f#\210\203\311\312!\210\313\211\207" [vhdl-progress-interval beg end vhdl-progress-info column vector count-lines 0 indent-region message "Indenting...done" nil] 5 (#$ . 235366) "r\nP"])
#@103 Indent whole buffer as VHDL code.
Calls `indent-region' for whole buffer and adds progress reporting.
(defalias 'vhdl-indent-buffer #[nil "\300ed\"\207" [vhdl-indent-region] 3 (#$ . 235738) nil])
#@44 Indent group of lines between empty lines.
(defalias 'vhdl-indent-group #[nil "\212\303\304\305#\203\306 \202\307 )\212\310\304\305#\203\306 \202!\311 )\312\n	\"*\207" [vhdl-align-group-separate end beg re-search-backward nil t point-marker point-min-marker re-search-forward point-max-marker vhdl-indent-region] 5 (#$ . 235940) nil])
#@145 Indent each line of the list starting just after point.
If optional arg ENDPOS is given, indent each line, stopping when
ENDPOS is encountered.
(defalias 'vhdl-indent-sexp #[(&optional endpos) "\212`\303\304\"\210`\305\n	\304#+\207" [endpos end beg vhdl-forward-sexp nil indent-region] 4 (#$ . 236293) nil])
#@46 Show syntactic information for current line.
(defalias 'vhdl-show-syntactic-information #[nil "\300\301\302 \"\210\303 \207" [message "Syntactic analysis: %s" vhdl-get-syntactic-context vhdl-keep-region-active] 3 (#$ . 236610) nil])
#@47 Check syntactic information for current line.
(defalias 'vhdl-regress-line #[(&optional arg) "\212\305\210\306\307`\310 \210`b\210)\311#\205\312u\210\313p!)\314 \305\315\316\n\"\210\f\204C\203C<\203C	\232\204p\317\320	#\210\202p\212\310 \210\321\322!\204o\305\210\306\307`\310 \210`b\210)\311#\203f`\323 |\210\324c\210\325\326	\"c\210)+\327 \207" [here expurgated actual expected arg nil search-backward " -- ((" beginning-of-line t 4 read vhdl-get-syntactic-context mapc #[(elt) "@\302>?\205\303	C\"\211\207" [elt expurgated (entity configuration package package-body architecture) append] 3] error "ERROR:  Should be: %s, is: %s" looking-at "^\\s-*\\(--.*\\)?$" line-end-position " -- " format "%s" vhdl-keep-region-active] 4 (#$ . 236849) "P"])
#@469 The format of this alist is (MODES [or MODE] REGEXP ALIGN-PATTERN SUBEXP).
It is searched in order.  If REGEXP is found anywhere in the first
line of a region to be aligned, ALIGN-PATTERN will be used for that
region.  ALIGN-PATTERN must include the whitespace to be expanded or
contracted.  It may also provide regexps for the text surrounding the
whitespace.  SUBEXP specifies which sub-expression of
ALIGN-PATTERN matches the white space to be expanded/contracted.
(defconst vhdl-align-alist '((vhdl-mode "^\\s-*\\(across\\|constant\\|quantity\\|signal\\|subtype\\|terminal\\|through\\|type\\|variable\\)[ 	]" "^\\s-*\\(across\\|constant\\|quantity\\|signal\\|subtype\\|terminal\\|through\\|type\\|variable\\)\\([ 	]+\\)" 2) (vhdl-mode ":[^=]" "\\([ 	]*\\):[^=]") (vhdl-mode ":[ 	]*\\(in\\|out\\|inout\\|buffer\\|\\)\\>" ":[ 	]*\\(in\\|out\\|inout\\|buffer\\|\\)\\([ 	]+\\)" 2) (vhdl-mode "[<:=]=" "\\([ 	]*\\)\\??[<:=]=" 1) (vhdl-mode "=>" "\\([ 	]*\\)=>" 1) (vhdl-mode "[<:=]=" "\\([ 	]*\\)\\??[<:=]=" 1) (vhdl-mode "[ 	]after\\>" "[^ 	]\\([ 	]+\\)after\\>" 1) (vhdl-mode "[ 	]when\\>" "[^ 	]\\([ 	]+\\)when\\>" 1) (vhdl-mode "[ 	]else\\>" "[^ 	]\\([ 	]+\\)else\\>" 1) (vhdl-mode "[ 	]across\\>" "[^ 	]\\([ 	]+\\)across\\>" 1) (vhdl-mode "[ 	]through\\>" "[^ 	]\\([ 	]+\\)through\\>" 1) (vhdl-mode "=>" "\\([ 	]*\\)=>" 1)) (#$ . 237631))
#@143 If REGEXP is not found on the first line of the region that clause
is ignored.  If this variable is non-nil, then the clause is tried anyway.
(defvar vhdl-align-try-all-clauses t (#$ . 238981))
#@55 Apply FUNCTION on group of lines between empty lines.
(defalias 'vhdl-do-group #[(function &optional spacing) "\212\305\306\307#\203\310\311!\210\312 \210`\202e)\212\313\306\307#\203&\310 \210`\202'd)\n	\f#*\207" [vhdl-align-group-separate end beg function spacing re-search-backward nil t beginning-of-line 2 back-to-indentation re-search-forward] 5 (#$ . 239181)])
#@86 Apply FUNCTION to the lines of a list surrounded by a balanced group of
parentheses.
(defalias 'vhdl-do-list #[(function &optional spacing) "\304\211\212\305\306\304\307#\310\311!\203 \304u\210\312 \210\305\306\304\307#\202	\2033\313 \210`	Tb\210\314\304w\210`)	\203@\n	#\202C\315\316!*\207" [end beg function spacing nil vhdl-re-search-backward "[()]" t looking-at ")" backward-sexp forward-list " 	\n
\f" error "ERROR:  Not within a list enclosed by a pair of parentheses"] 4 (#$ . 239565)])
#@52 Apply FUNCTION to block of lines with same indent.
(defalias 'vhdl-do-same-indent #[(function &optional spacing) "\305 \306\211\212o\204+\307\310!\204\305 \nU\203+\307\311!\204$\312 \210`\313\314!\210\202)\212m\204T\307\310!\204>\305 \nU\203T\307\311!\203K\313\315!\210\202-\313\315!\210`\202-)	\f#+\207" [end beg indent function spacing current-indentation nil looking-at "^\\s-*\\(--.*\\)?$" "^\\s-*$" back-to-indentation beginning-of-line 0 2] 4 (#$ . 240079)])
#@307 Attempt to align a range of lines based on the content of the
lines.  The definition of `alignment-list' determines the matching
order and the manner in which the lines are aligned.  If ALIGNMENT-LIST
is not specified `vhdl-align-alist' is used.  If INDENT is non-nil,
indentation is done before aligning.
(defalias 'vhdl-align-region-1 #[(begin end &optional spacing alignment-list indent) "\206	\n\206\306\212\307\211
b\210\310 b\210\311 \210`\211\203-\312\f
\307#\210+\313!\314\315 \307\211\211\316 !\210\317\320!\203\205\320 \321@A\"\211\203\205@\322\323!>\203|B\324\322\307#\210A\211\204`\325\216\205\341\212b\210\307\326 !\"@\211\"@<\203\254#\"@>\204\265#\"@=\203\330$\204\306\327\"A@!\314#\203\330\330
\"AA@\"AAA@\n%\210A+\202\207.\207" [alignment-list vhdl-align-alist spacing indent bol end 1 nil point-marker beginning-of-line indent-region copy-alist t syntax-table set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) point-at-eol re-search-forward vhdl-align-region-2 begin copy overlay overlay-intangible-list overlay-all-list current-syntax-table case-fold-search vhdl-mode-ext-syntax-table eol element major-mode vhdl-align-try-all-clauses] 7 (#$ . 240571) "r\np"])
#@400 Align a range of lines from BEGIN to END.  The regular expression
MATCH must match exactly one field: the whitespace to be
contracted/expanded.  The alignment column will equal the
rightmost column of the widest whitespace block.  SPACING is
the amount of extra spaces to add to the calculated maximum required.
SPACING defaults to 1 so that at least one space is inserted after
the token in MATCH.
(defalias 'vhdl-align-region-2 #[(begin end match &optional substr spacing) "\206\306	\206\306\212\307\310\211\307\211\211b\210\311 \312 \210`\211\fW\203|\212\313\314#\203m\212\310\224b\210\307u\210\315 ?\205R\316 ?\205R\317 ?)\203m\320\321!\204m	\224\fZ\211V\203m)\307y\210`\311 
T\202*\211b\210\311 
\310V\205\362\313\314#\203\340\212\310\224b\210\307u\210\315 ?\205\253\316 ?\205\253\317 ?)\203\340\320\321!\204\340\310\224\212\322 \210`)V\203\340	\225	\224Z	\224\fZ	\224b\210\323\n!\210\324\325Z\\\"\210\312 \210\307y\210`\311 
S\211\202\206.\207" [spacing substr width eol bol lines 1 nil 0 point-at-eol beginning-of-line vhdl-re-search-forward t vhdl-in-literal vhdl-in-quote-p vhdl-in-extended-identifier-p looking-at "\\s-*$" back-to-indentation delete-char insert-char 32 max distance begin end match] 7 (#$ . 242090)])
#@49 Align region, treat groups of lines separately.
(defalias 'vhdl-align-region-groups #[(beg end &optional spacing no-message no-comments) "\212\306\211\nb\210\307 \210\310 `b\210\310 \311\n\"\210\f\2040
\2030\312\313e\n\"\313e\"\314#\315\n\316#\210\nb\210\204R\317\n#\210\204\241\320\n\"\210\202\241\nW\203\204\321\316#\203\204\310 \317\n#\210\204u\320\n\"\210\322\323\324 \"\210T\211b\210\202R\nW\203\241\317\n#\210\204\233\320\n\"\210\322\323\324 \"\210\203\253\325	\"\210\f?\205\274
\203\270\326\327!\210\306\211+\207" [pos orig beg end no-message vhdl-progress-interval nil beginning-of-line point-marker untabify vector count-lines 0 vhdl-fixup-whitespace-region t vhdl-align-region-1 vhdl-align-inline-comment-region-1 re-search-forward vhdl-update-progress-info "Aligning" vhdl-current-line tabify message "Aligning...done" vhdl-progress-info vhdl-align-groups spacing no-comments vhdl-align-group-separate vhdl-indent-tabs-mode] 6 (#$ . 243396) "r\nP"])
#@76 Align region, treat blocks with same indent and argument lists separately.
(defalias 'vhdl-align-region #[(beg end &optional spacing) "\204\n\306	\n#\207\212	\307\211\203$\310\311e	\"\311e\n\"\312#\nb\210\313 b\210`\nW\203\304\212\314``\307\210`b\210)\")A@\211\203]b\210\315 \210`\316\317!\210\202\270\320 ``\321y\210`b\210)\316\317!\210`\nW\203\270\322\323!\204\207\320 
U\203\270\212\314``\307\210`b\210)\"@)\312X\203\270\322\324!\204\261`\321y\210`b\210)\316\317!\210\202t\306\f\325\211%\210\202.\326	\n$\210\203\325\327\330!\210\307\211,\207" [vhdl-align-same-indent beg end spacing cur-end indent vhdl-align-region-groups nil vector count-lines 0 point-marker parse-partial-sexp forward-sexp beginning-of-line 2 current-indentation 1 looking-at "^\\s-*\\(--.*\\)?$" "^\\s-*$" t vhdl-align-inline-comment-region message "Aligning...done" cur-beg vhdl-progress-interval vhdl-progress-info here noninteractive] 6 (#$ . 244421) "r\nP"])
#@43 Align group of lines between empty lines.
(defalias 'vhdl-align-group #[(&optional spacing) "\301\302\"\207" [spacing vhdl-do-group vhdl-align-region] 3 (#$ . 245429) nil])
#@74 Align the lines of a list surrounded by a balanced group of parentheses.
(defalias 'vhdl-align-list #[(&optional spacing) "\301\302\"\207" [spacing vhdl-do-list vhdl-align-region-groups] 3 (#$ . 245609) nil])
#@40 Align block of lines with same indent.
(defalias 'vhdl-align-same-indent #[(&optional spacing) "\301\302\"\207" [spacing vhdl-do-same-indent vhdl-align-region-groups] 3 (#$ . 245825) nil])
#@63 Align the lines within the declarative part of a design unit.
(defalias 'vhdl-align-declarations #[(&optional spacing) "\306\211\307\310 \306\211\211\311!\210\312\313!\203E\313 \314\f@\fA\"\211\203E\f@\315\316\n!>\203>\nB\317\n\315\306#\210\fA\211\204)\320\216\212\321\322\306\307#\203c\323\324!\226\325\235\204c`\326\327\306\307#\210`.	\203r\330	#\202u\331\332!*\207" [end beg overlay overlay-intangible-list overlay-all-list current-syntax-table nil t syntax-table set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) re-search-backward "^\\(architecture\\|begin\\|configuration\\|end\\|entity\\|package\\)\\>" match-string 1 ("BEGIN" "END") re-search-forward "^\\(begin\\|end\\)\\>" vhdl-align-region-groups error "ERROR:  Not within the declarative part of a design unit" case-fold-search vhdl-mode-ext-syntax-table spacing] 6 (#$ . 246021) nil])
#@15 Align buffer.
(defalias 'vhdl-align-buffer #[nil "\300ed\"\207" [vhdl-align-region] 3 (#$ . 247145) nil])
#@34 Align inline comments in region.
(defalias 'vhdl-align-inline-comment-region-1 #[(beg end &optional spacing) "\212\306\307\211\211\211\211\211\211\211 !\"#$%\206 \310%\311\312 \307\211\211&'()*\313+!\210\314\315!\203t\315 (\316(@(A\"\211(\203t(@&\317\320&!>\203k&'B'\321&\317\307#\210(A\211(\204O\322\216,b\210`-W\203\302\323\324!\204\273\323\325!\203\273\212\310\224b\210\326 )\204\273\327\225\327\224Z%\\\310\225\310\224Z
$]$\f#]#
\fB\"B\"\330\310!\210\202z\331\"\332\"\211\"\211.@@)C!\"A\211\"\203
\"\211.@@)!@U\204\n
!@\"\211.@A)\\/X\204\n
\"\211.@@)!B!\"A\211\"\204\334,b\210`-W\205\316
\307\323\324!\204\305
\323\333!\2037
\212\334\224b\210\326 )\203G
\323\335!\203\305
\310\225\310\224ZY\203\305
\327\225\327\224Z%\\\334\225\334\224Z\327\224\327\225U\310\225b\210\310\224\310\225|\210\336\337%\"\210! 	\203\205
\n\203\205
\f/\nZX\203\205
\n\202\301
$#\\/X\203\225
$\202\301

X\203\250
\f/ZX\203\250
\202\301
 \203\276
 @
W\203\276
 A\211 \204\255
 @\211j\210\330\310!\210\202
.\207" [comment-column no-code prev-start cur-start length start 0 nil 2 t syntax-table set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) looking-at "^\\s-*\\(begin\\|end\\)\\>" "^\\(.*[^ 	\n
\f-]+\\)\\s-*\\(--.*\\)$" vhdl-in-literal 1 beginning-of-line sort #[(a b) "@	@V\207" [a b] 2] "^\\(.*[^ 	\n
\f-]+\\)\\(\\s-*\\)\\(--.*\\)$" 3 "^\\(\\)\\(\\s-*\\)\\(--.*\\)$" insert-char 32 tmp-list start-list comment-list length-max start-max spacing overlay overlay-intangible-list overlay-all-list current-syntax-table case-fold-search vhdl-mode-ext-syntax-table beg end x end-comment-column] 11 (#$ . 247257)])
#@148 Align inline comments within a region.  Groups of code lines separated by
empty lines are aligned individually, if `vhdl-align-groups' is non-nil.
(defalias 'vhdl-align-inline-comment-region #[(beg end &optional spacing no-message) "\212\306\211\nb\210\307 \210\310 `b\210\310 \311\n\"\210\f\204#\312\313!\210\nb\210
\2044\314\n#\210\202c\nW\203V\315\316#\203V\310 \314\n#\210T\211b\210\2024\nW\203c\314\n#\210\203m\317	\"\210\f?\205u\312\320!+\207" [pos orig beg end no-message vhdl-align-groups nil beginning-of-line point-marker untabify message "Aligning inline comments..." vhdl-align-inline-comment-region-1 re-search-forward t tabify "Aligning inline comments...done" spacing vhdl-align-group-separate vhdl-indent-tabs-mode] 5 (#$ . 249199) "r\nP"])
#@68 Align inline comments within a group of lines between empty lines.
(defalias 'vhdl-align-inline-comment-group #[(&optional spacing) "\212`\305\211\306\305\307#\203\310 \202d\nb\210\311\305\307#\203%`\202&e\312	\"\210\313\314!\210\315	\"\210\f\203>\316	\"\210\313\317!,\207" [end beg start vhdl-align-group-separate vhdl-indent-tabs-mode nil re-search-forward t point-marker re-search-backward untabify message "Aligning inline comments..." vhdl-align-inline-comment-region-1 tabify "Aligning inline comments...done"] 4 (#$ . 249998) nil])
#@146 Align inline comments within buffer.  Groups of code lines separated by
empty lines are aligned individually, if `vhdl-align-groups' is non-nil.
(defalias 'vhdl-align-inline-comment-buffer #[nil "\300ed\"\207" [vhdl-align-inline-comment-region] 3 (#$ . 250561) nil])
#@196 Fixup whitespace in region.  Surround operator symbols by one space,
eliminate multiple spaces (except at beginning of line), eliminate spaces at
end of line, do nothing in comments and strings.
(defalias 'vhdl-fixup-whitespace-region #[(beg end &optional no-message) "\204\303\304!\210\212	b\210\305 \nb\210\306\307	\310#\2032\311\312!\203'\312\225b\210\202\313\314\315\211\211\316%\210\202\nb\210\306\317	\310#\203Q\311\312!\203J\312\225b\210\2025\313\320!\210\2025\nb\210\306\321	\310#\203p\311\312!\203i\312\225b\210\202T\313\320!\210\202T\nb\210\306\322	\310#\203\237\311\312!\204\215\323\224\212\324 \210`)X\203\224\323\225b\210\202s\313\325!\210\316\225b\210\202s\nb\210\326\327!\203\260\306\327	\310#\204\242\326\330!\203\276\306\330	\310#\204\242\326\331!\203\314\306\332	\310#\204\242\326\333!\203\343\306\333	\310#\203\343\313\334\315\211#\210\202\242\326\335!\203\372\306\335	\310#\203\372\313\336\315\211#\210\202\242\326\337!\203
\306\337	\310#\204\242\326\340!\203
\306\341	\310#\203
\313\342\315\211#\210\202\242\326\341!\2036
\306\341	\310#\2036
\313\343\315\211#\210\202\242\326\344!\203D
\306\344	\310#\204\242\306\345	\310#\204\242)?\205U
\303\346!\207" [no-message end beg message "Fixing up whitespace..." point-marker re-search-forward "\\(--.*\n\\|\"[^\"\n]*[\"\n]\\|'.'\\|\\\\[^\\\n]*[\\\n]\\)\\|\\(\\s-*\\([,;]\\)\\)" t match-string 1 replace-match "\\3 " nil 2 "\\(--.*\n\\|\"[^\"\n]*[\"\n]\\|'.'\\|\\\\[^\\\n]*[\\\n]\\)\\|\\((\\)\\s-+" "\\2" "\\(--.*\n\\|\"[^\"\n]*[\"\n]\\|'.'\\|\\\\[^\\\n]*[\\\n]\\|^\\s-+\\)\\|\\s-+\\()\\)" "\\(--.*\n\\|\"[^\"\n]*[\"\n]\\|'.'\\|\\\\[^\\\n]*[\\\n]\\)\\|\\(\\([^/:<>=]\\)\\(:\\|\\??=\\|\\??<<\\|\\??>>\\|\\??<\\|\\??>\\|:=\\|\\??<=\\|\\??>=\\|=>\\|\\??/=\\|\\?\\?\\)\\([^=>]\\|$\\)\\)" 0 back-to-indentation "\\3 \\4 \\5" looking-at "--.*\n" "--.*" "\"" "\"[^\"\n]*[\"\n]" "\\s-+$" "" "\\s-+;" ";" "^\\s-+" "\\s-+--" "\\s-+" "  " " " "-" "[^ 	\"-]+" "Fixing up whitespace...done"] 6 (#$ . 250835) "r"])
#@184 Fixup whitespace in buffer.  Surround operator symbols by one space,
eliminate multiple spaces (except at beginning of line), eliminate spaces at
end of line, do nothing in comments.
(defalias 'vhdl-fixup-whitespace-buffer #[nil "\300ed\"\207" [vhdl-fixup-whitespace-region] 3 (#$ . 252852) nil])
#@232 Beautify region by applying indentation, whitespace fixup, alignment, and
case fixing to a region.  Calls functions `vhdl-indent-buffer',
`vhdl-align-buffer' (option `vhdl-align-groups' set to non-nil), and
`vhdl-fix-case-buffer'.
(defalias 'vhdl-beautify-region #[(beg end) "\212b\210\303 )\304	\"\210\305\306	\"\210)\307	\"\207" [end beg vhdl-align-groups point-marker vhdl-indent-region t vhdl-align-region vhdl-fix-case-region] 3 (#$ . 253156) "r"])
#@158 Beautify buffer by applying indentation, whitespace fixup, alignment, and
case fixing to entire buffer.  Calls `vhdl-beautify-region' for the entire
buffer.
(defalias 'vhdl-beautify-buffer #[nil "\301ed\"\210\205\302 \207" [noninteractive vhdl-beautify-region save-buffer] 3 (#$ . 253623) nil])
#@34 Fill lines for a region of code.
(defalias 'vhdl-fill-region #[(beg end &optional arg) "\212b\210	\203
\305 \202ib\210\306 \307\"\210\310\"\210\311S\312\313$\210\314\"\210b\210\315\316\317#\205Ri\fV\203/\320u\210\321\316\317#\203/\322\323!\210\nj\210\202/*\207" [beg arg margin end vhdl-end-comment-column current-indentation point-marker vhdl-comment-kill-region vhdl-comment-kill-inline-region subst-char-in-region 10 32 vhdl-fixup-whitespace-region re-search-forward "\\s-" t -1 re-search-backward replace-match "\n"] 5 (#$ . 253927) "r\np"])
#@42 Fill group of lines between empty lines.
(defalias 'vhdl-fill-group #[nil "\300\301!\207" [vhdl-do-group vhdl-fill-region] 2 (#$ . 254501) nil])
#@73 Fill the lines of a list surrounded by a balanced group of parentheses.
(defalias 'vhdl-fill-list #[nil "\300\301!\207" [vhdl-do-list vhdl-fill-region] 2 (#$ . 254652) nil])
#@52 Fill the lines of block of lines with same indent.
(defalias 'vhdl-fill-same-indent #[nil "\300\301!\207" [vhdl-do-same-indent vhdl-fill-region] 2 (#$ . 254832) nil])
#@45 Update sensitivity list of current process.
(defalias 'vhdl-update-sensitivity-list-process #[nil "\212\306\307 \310\211\211\311
!\210\312\313!\203@\313 \314\n@\nA\"\211\203@\n@\315\316!>\2039	B\317\315\310#\210\nA\211\204$\320\216\310\210\321\322\310\306#\203`\323\324!\226\325\232\203`\212\326\327\310\306#)\204f\330\331!\202p\332\333!\210\334 \210\332\335!.\207" [overlay overlay-intangible-list overlay-all-list current-syntax-table case-fold-search vhdl-mode-ext-syntax-table t syntax-table nil set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) re-search-backward "^\\s-*\\(\\w+[ 	\n
\f]*:[ 	\n
\f]*\\)?\\(process\\|end\\s-+process\\)\\>" match-string 2 "PROCESS" re-search-forward "^\\s-*end\\s-+process\\>" error "ERROR:  Not within a process" message "Updating sensitivity list..." vhdl-update-sensitivity-list "Updating sensitivity list...done"] 6 (#$ . 255005) nil])
#@61 Update sensitivity list of all processes in current buffer.
(defalias 'vhdl-update-sensitivity-list-buffer #[nil "\212\306\307 \310\211\211\311
!\210\312\313!\203@\313 \314\n@\nA\"\211\203@\n@\315\316!>\2039	B\317\315\310#\210\nA\211\204$\320\216eb\210\321\322!\210\323\324\310\306#\203]\325\224b\210\310\326\327\217\210\202I\321\330!.\207" [overlay overlay-intangible-list overlay-all-list current-syntax-table case-fold-search vhdl-mode-ext-syntax-table t syntax-table nil set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) message "Updating sensitivity lists..." re-search-forward "^\\s-*\\(\\w+[ 	\n
\f]*:[ 	\n
\f]*\\)?process\\>" 0 (vhdl-update-sensitivity-list) ((error)) "Updating sensitivity lists...done"] 6 (#$ . 256151) nil])
#@26 Update sensitivity list.
(defalias 'vhdl-update-sensitivity-list #[nil "`\306\307\310\311#\312\313\310\311#\310\314\315!\204\316\317!\202\362
	b\210\320\321\n\311#\203-\316\322!\202\362
\323 \324\310\211\211\211\211\211\211\211\211\211456789:;<=b\210\306\325	\311#\210\326\327!\204e`6\202\232\306\330\310\311#6\331\225b\210\332 \210`S56b\210\306\3335\311#\203\232\314\334!\2278B\2118\203\232\306\3355\311#\204{\336=8\"7	b\210\306\337\n\311#\2114\203\324\306\340\n\311#\341\3424\311#\203\245
b\210\343v\210\344 \210
`BB\345 \210\202\245<\203\214
	b\210\346<@@!\2114\203\203
\346<@A@!\211\203\203
4b\210\347 \204\334\2031
\211>\203
`>\211?@@)W\203
>A\211>\204
>\205-
`>\211?@A)W)\204\334\320\350
\311#\203\334\314\331!;@\203H
\314\315!:\314\351!\204|
\314\352!\203]
\314\352!\227\353\235\203|
;\2277\235\203|
\354;:P9\"\204|
;:P9B9\331\225b\210\2021
<A\211<\204\3316b\2105\203\236
65|\210\202\251
9\203\251
\355c\210\343u\210\3569\357\"\2119\205\360
i9@c\2109A\2119\205\360
\360c\210\361i9@G\315#AX\203\333
\362c\210\202\341
\363c\210\fj\2109@c\2109A\2119\204\304
\310.\f,\207" [seq-region-list proc-mid proc-end proc-beg margin end re-search-forward "^\\s-*end\\s-+process\\>" nil t vhdl-re-search-backward "\\(\\(\\<begin\\>\\)\\|^\\s-*process\\>\\)" match-string 2 error "ERROR:  No 'begin' keyword found" vhdl-re-search-forward "\\<wait\\>" "ERROR:  Process with wait statement, sensitivity list not generated" vhdl-get-visible-signals (((re-search-forward "[<:]=" proc-end t) (re-search-forward ";\\|\\<\\(then\\|loop\\|report\\|severity\\|is\\)\\>" proc-end t)) ((re-search-forward "^\\s-*if\\>" proc-end t) (re-search-forward "\\<then\\>" proc-end t)) ((re-search-forward "\\<elsif\\>" proc-end t) (re-search-forward "\\<then\\>" proc-end t)) ((re-search-forward "^\\s-*while\\>" proc-end t) (re-search-forward "\\<loop\\>" proc-end t)) ((re-search-forward "\\<\\(exit\\|next\\)\\s-+\\w+\\s-+when\\>" proc-end t) (re-search-forward ";" proc-end t)) ((re-search-forward "\\<assert\\>" proc-end t) (re-search-forward "\\(\\<report\\>\\|\\<severity\\>\\|;\\)" proc-end t)) ((re-search-forward "^\\s-*case\\>" proc-end t) (re-search-forward "\\<is\\>" proc-end t)) ((and (re-search-forward "^\\s-*\\(\\w\\|\\.\\)+[ 	\n
\f]*(" proc-end t) (1- (point))) (progn (backward-char) (forward-sexp) (while (looking-at "(") (forward-sexp)) (point)))) "\\<process\\>" looking-at "[ 	\n
\f]*(" "\\([ 	\n
\f]*\\)([ 	\n
\f]*" 1 forward-sexp "\\(\\w+\\)" 0 "\\s-*,\\s-*" append "^\\s-*\\(els\\)?if\\>" "\\<then\\>" re-search-backward "\\('event\\|\\<\\(falling\\|rising\\)_edge\\)\\>" -1 vhdl-forward-sexp beginning-of-line eval vhdl-in-literal "[^'\".]\\<\\([a-zA-Z]\\w*\\)\\(\\(\\.\\w+\\|[ 	\n
\f]*([^)]*)\\)*\\)[ 	\n
\f]*\\('\\(\\w+\\)\\|\\(=>\\)\\)?" 6 5 ("event" "last_event" "transaction") member-ignore-case " ()" sort string< "," + " " "\n" beg sens-end sens-beg signal-list sens-list read-list field name scan-regions-list visible-list tmp-list x vhdl-array-index-record-field-in-sensitivity-list end-comment-column] 13 (#$ . 257153)])
#@47 Get all signals visible in the current block.
(defalias 'vhdl-get-visible-signals #[nil "\306\211\211\211\211\307\310 \306\211\211@ABC\311D!\210\312\313!\203W\313 A\314A@AA\"\211A\203WA@\315\316
!>\203N
@B@\317
\315\306#\210AA\211A\2046\320\216\212\321\322\306\307#\203s\323\324!\226\325\232\204s\323\326!\211\204w\327\330!\210)\212eb\210\331\332	\333Q\306\307#\204\224\334E	\307#\335\336\337 !Q\204R
\307\310 \306\211\211@ABC\311D!\210\312\313!\203\345\313 A\314A@AA\"\211A\203\345A@\315\316
!>\203\334
@B@\317
\315\306#\210AA\211A\204\304\340\216eb\210\331\332	\333Q\306\307#\204\375\327\341	\"\210\202M
\342\343\212\331\344\306\307#)\307#\211\203M
\212\345u\210\346 \210`)\347 \210`W\203M
\350\351!\203*
\352\225b\210\350\353!\203A
\323\324!\227\nB\352\225b\210\347 \210\202*
\331\354\324#\210\347 \210\202
.\202\210
\355!\204\210
p\356!\306FGHG\203n
Gq\204u
\306\357\360\217\203z
\361\362\363\217\210F\203\203
\364p!\210Hq\210+)\212\321\322\306\307#\211\203\247
\323\324!\226\325\232\204\247
\331\365\306\307#\211\204\256
\327\366!\210\202\374
\fb\210\331\367\307#\203\374
\370\f`\"@\352U\203\261
\323\326!\203\335
\350\371!\203\367
\323\324!\227\nB\352\225b\210\202\311
\350\372!\203\367
\323\326!\227\n\235\203\367
\323\324!\227\nB\352\225b\210`\202\261
)\212\321\373\306\307#\211\203\323\326!\203\326\225b\210\374 \210\321\375\306\307#\210\202\376
\f\203\200\331\376\306\307#\211\203\200\fb\210\331\367\307#\203z\370\f`\"@\352U\203/\323\326!\203[\350\377!\203/\323\324!\227\nB\352\225b\210\202G\350\201I!\203/\323\326!\227\n\235\203/\323\324!\227\nB\352\225b\210\202/\fb\210\202\376
)\n.\207" [file-name entity-name signal-list end beg overlay nil t syntax-table set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) re-search-backward "^\\(architecture\\s-+\\w+\\s-+of\\s-+\\(\\w+\\)\\|end\\)\\>" match-string 1 "END" 2 error "ERROR:  Not within an architecture" re-search-forward "^entity\\s-+" "\\>" vhdl-replace-string "." file-name-extension buffer-file-name ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) #1="ERROR:  Entity \"%s\" not found:\n  --> see option `vhdl-entity-file-name'" vhdl-re-search-forward #2="\\<port[ 	\n
\f]*(" #3="^end\\>" -1 forward-sexp vhdl-forward-syntactic-ws looking-at #4="signal[ 	\n
\f]+" 0 #5="\\(\\w+\\)[ 	\n
\f,]+" #6=";" file-directory-p find-buffer-visiting (byte-code "\302!q\210\303\304!\210\305\306\307\310 #\210\305\311\312\310 #\210\305\313\312\310 #\210\305\314\315\310 #\210\303\207" [file-name file-opened create-file-buffer t vhdl-insert-file-contents modify-syntax-entry 45 ". 12" syntax-table 10 ">" 13 95 "w"] 4) ((error (byte-code "\203\303p!\210	q\210\304\305\n\"\207" [file-opened source-buffer file-name kill-buffer error "ERROR:  File cannot be opened: \"%s\""] 3))) info (byte-code "\306\307 \310\211\211\311
!\210\312\313!\203?\313 \314\n@\nA\"\211\203?\n@\315\316!>\2038	B\317\315\310#\210\nA\211\204#\320\216eb\210\321\322#\323Q\310\306#\204Y\324\325#\"\210\202\257\326\327\212\321\330\310\306#)\306#\211$\203\257\212\331u\210\332 \210`)%\333 \210`%W\203\257\334\335!\203\211\336\225b\210\334\337!\203\242\340\341!\227&B&\336\225b\210\333 \210\202\211\321\342%\341#\210\333 \210\202x.\310\207" [overlay overlay-intangible-list overlay-all-list current-syntax-table case-fold-search vhdl-mode-ext-syntax-table t syntax-table nil set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) re-search-forward "^entity\\s-+" "\\>" error #1# vhdl-re-search-forward #2# #3# -1 forward-sexp vhdl-forward-syntactic-ws looking-at #4# 0 #5# match-string 1 #6# entity-name beg end signal-list] 7) ((error (byte-code "\203\304p!\210	q\210\305\n\211A@)!\207" [file-opened source-buffer info x kill-buffer error] 3))) kill-buffer "^begin\\>" "ERROR:  No architecture declarative part found" "^\\s-*\\(\\(signal\\)\\|alias\\)\\>" parse-partial-sexp "[ 	\n
\f,]+\\(\\w+\\)" "[ 	\n
\f]+\\(\\w+\\)[^;]*\\<is[ 	\n
\f]+\\(\\w+\\)" "^\\s-*\\(\\w+\\s-*:\\s-*block\\|\\(end\\)\\s-+block\\)\\>" vhdl-backward-sexp "^\\s-*\\w+\\s-*:\\s-*block\\>" "^\\s-*begin\\>" "[ 	\n,]+\\(\\w+\\)" overlay-intangible-list overlay-all-list current-syntax-table case-fold-search vhdl-mode-ext-syntax-table vhdl-entity-file-name file-opened visiting-buffer source-buffer "[ 	\n]+\\(\\w+\\)[^;]*\\<is[ 	\n]+\\(\\w+\\)"] 7 (#$ . 260287)])
#@49 Fix all generic/port clauses in current buffer.
(defalias 'vhdl-fix-clause-buffer #[nil "\212\306\307 \310\211\211\311
!\210\312\313!\203@\313 \314\n@\nA\"\211\203@\n@\315\316!>\2039	B\317\315\310#\210\nA\211\204$\320\216eb\210\321\322!\210\323\324\310\306#\203]\325\225b\210\310\326\327\217\210\202I\321\330!.\207" [overlay overlay-intangible-list overlay-all-list current-syntax-table case-fold-search vhdl-mode-ext-syntax-table t syntax-table nil set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) message "Fixing generic/port clauses..." re-search-forward "^\\s-*\\(generic\\|port\\)[ 	\n
\f]*(" 0 (vhdl-fix-clause) ((error)) "Fixing generic/port clauses...done"] 6 (#$ . 265321) nil])
#@53 Fix closing parenthesis within generic/port clause.
(defalias 'vhdl-fix-clause #[nil "\212\306\307 \310\211\211\311
!\210\312\313!\203@\313 \314\n@\nA\"\211\203@\n@\315\316!>\2039	B\317\315\310#\210\nA\211\204$\320\216`\310\211%&'\310\210\321\322\310\306#\204\\\323\324!\202\313\325\225b\210`S&\326 \210\327\330!\203\325\225Sb\210\331 %\310u\210\326 \210\202g%b\210'\332 V\203\217\323\324!\210\212\333 \210\327\334!)\203\247\335 \210\336 \210\331 %\337c\210&b\210\310\340\341\217\210`%W\203\276\342\343!\210\202\247`%V\205\313%b\210\344c.\n\207" [overlay overlay-intangible-list overlay-all-list current-syntax-table case-fold-search vhdl-mode-ext-syntax-table t syntax-table nil set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) re-search-backward "^\\s-*\\(generic\\|port\\)[ 	\n
\f]*(" error "ERROR:  Not within a generic/port clause" 0 vhdl-forward-syntactic-ws looking-at "\\w+\\([ 	\n
\f]*,[ 	\n
\f]*\\w+\\)*[ 	\n
\f]*:[ 	\n
\f]*\\w+[^;]*;" point-marker point-at-eol beginning-of-line "^\\s-*);" vhdl-line-kill vhdl-backward-syntactic-ws ";" (forward-sexp) ((error (byte-code "db\207" [] 1))) delete-char -1 ")" end beg pos] 6 (#$ . 266276) nil])
#@45 Remove trailing spaces in the whole buffer.
(defalias 'vhdl-remove-trailing-spaces #[nil "\301 \302\216\212eb\210\303\304d\305#\205\306 \204	\307\310\311\211#\210\202	+\207" [save-match-data-internal match-data ((byte-code "\301\302\"\207" [save-match-data-internal set-match-data evaporate] 3)) re-search-forward "[ 	]+$" t vhdl-in-literal replace-match "" nil] 4 (#$ . 267715) nil])
#@51 Syntax of prompt inserted by template generators.
(defconst vhdl-template-prompt-syntax "[^ =<>][^<>@.\n]*[^ =<>]" (#$ . 268112))
#@118 Indicates whether a template has been invoked by a hook or by key or menu.
Used for undoing after template abortion.
(defvar vhdl-template-invoked-by-hook nil (#$ . 268249))
(defalias 'vhdl-character-to-event #[(arg) "\300\207" [nil] 1])
(byte-code "\300\301\302\303!\203\f\303\202
\304\"\207" [defalias vhdl-character-to-event fboundp character-to-event identity] 4)
#@92 Return the working library name of the current project or "work" if no
project is defined.
(defalias 'vhdl-work-library #[nil "\303\304\305	\"8\206\n!\207" [vhdl-project-alist vhdl-project vhdl-default-library vhdl-resolve-env-variable 6 aget] 5 (#$ . 268625)])
#@275 Non-nil if Vhdl-Electric mode is enabled.
See the command `vhdl-electric-mode' for a description of this minor mode.
Setting this variable directly does not take effect;
either customize it (see the info node `Easy Customization')
or call the function `vhdl-electric-mode'.
(custom-declare-variable 'vhdl-electric-mode nil '(#$ . 268897) :set 'custom-set-minor-mode :initialize 'custom-initialize-default :group 'vhdl-electric :type 'boolean)
#@176 Toggle VHDL electric mode.
With a prefix argument ARG, enable the mode if ARG is positive,
and disable it otherwise.  If called from Lisp, enable it if ARG
is omitted or nil.
(defalias 'vhdl-electric-mode #[(&optional arg) "\303 	\304=\203\n?\202\305	!\306V\307\310\n\203\311\202\312\"\210\313\314!\203D\315\302!\210\303 \2037\303 \232\203D\316\317\n\203A\320\202B\321\"\210)\322 \210\n\207" [#1=#:last-message arg vhdl-electric-mode current-message toggle prefix-numeric-value 0 run-hooks vhdl-electric-mode-hook vhdl-electric-mode-on-hook vhdl-electric-mode-off-hook called-interactively-p any customize-mark-as-set message "Vhdl-Electric mode %sabled" "en" "dis" force-mode-line-update] 3 (#$ . 269347) (list (or current-prefix-arg 'toggle))])
(byte-code "\301\302\303\304\300!\205\n\303\211%\210\305\306\303\307\310\311\312\313\314\315\316\317&\207" [vhdl-electric-mode-map add-minor-mode vhdl-electric-mode nil boundp custom-declare-variable vhdl-stutter-mode "Non-nil if Vhdl-Stutter mode is enabled.\nSee the command `vhdl-stutter-mode' for a description of this minor mode.\nSetting this variable directly does not take effect;\neither customize it (see the info node `Easy Customization')\nor call the function `vhdl-stutter-mode'." :set custom-set-minor-mode :initialize custom-initialize-default :group vhdl-stutter :type boolean] 12)
#@178 Toggle VHDL stuttering mode.
With a prefix argument ARG, enable the mode if ARG is positive,
and disable it otherwise.  If called from Lisp, enable it if ARG
is omitted or nil.
(defalias 'vhdl-stutter-mode #[(&optional arg) "\303 	\304=\203\n?\202\305	!\306V\307\310\n\203\311\202\312\"\210\313\314!\203D\315\302!\210\303 \2037\303 \232\203D\316\317\n\203A\320\202B\321\"\210)\322 \210\n\207" [#1=#:last-message arg vhdl-stutter-mode current-message toggle prefix-numeric-value 0 run-hooks vhdl-stutter-mode-hook vhdl-stutter-mode-on-hook vhdl-stutter-mode-off-hook called-interactively-p any customize-mark-as-set message "Vhdl-Stutter mode %sabled" "en" "dis" force-mode-line-update] 3 (#$ . 270719) (list (or current-prefix-arg 'toggle))])
(byte-code "\301\302\303\304\300!\205\n\303\211%\207" [vhdl-stutter-mode-map add-minor-mode vhdl-stutter-mode nil boundp] 6)
#@82 -- starts a comment, --- draws a horizontal line,
---- starts a display comment.
(defalias 'vhdl-electric-dash #[(count) "\203c\306 \204c	\203	`U\203\307\nb\210\310\307!\210\311 \207h\312U\204)\313!\207\313!\210\314\315!\210\316 \211\312U\203Z\317 \210\314\320!\210\316 \211\312U\203P\311\321!\202V\322\f!C\211)\202a\322\f!C\323 )\207\313!\207" [vhdl-stutter-mode abbrev-start-location last-abbrev-location count next-input unread-command-events vhdl-in-literal nil beginning-of-line vhdl-comment-display 45 self-insert-command message "Enter '-' for horiz. line, 'CR' for commenting-out code, else enter comment" read-char vhdl-comment-display-line "Enter '-' for display comment, else continue coding" t vhdl-character-to-event vhdl-comment-insert] 3 (#$ . 271611) "p"])
#@27 '[' --> '(', '([' --> '['
(defalias 'vhdl-electric-open-bracket #[(count) "\203#	\302U\203#\303 \204#h\304U\203\305\306!\210\307\310\302\"\207\307\304\302\"\207\311	!\207" [vhdl-stutter-mode count 1 vhdl-in-literal 40 delete-char -1 insert-char 91 self-insert-command] 3 (#$ . 272410) "p"])
#@27 ']' --> ')', ')]' --> ']'
(defalias 'vhdl-electric-close-bracket #[(count) "\203)	\302U\203)\303 \204)h\304U\203!\305\306!\210\307\310\302\"\210\202&\307\304\302\"\210\311 \207\312	!\207" [vhdl-stutter-mode count 1 vhdl-in-literal 41 delete-char -1 insert-char 93 blink-matching-open self-insert-command] 3 (#$ . 272713) "p"])
#@10 '' --> "
(defalias 'vhdl-electric-quote #[(count) "\203#	\303U\203#\304 \204#h\nU\203\305\306!\210\307\310\303\"\207\307\311\303\"\207\312	!\207" [vhdl-stutter-mode count last-input-event 1 vhdl-in-literal delete-char -1 insert-char 34 39 self-insert-command] 3 (#$ . 273052) "p"])
#@34 ';;' --> ' : ', ': ;' --> ' := '
(defalias 'vhdl-electric-semicolon #[(count) "\203A	\305U\203A\306 \204Ah\nU\203)\307\310!\210h\311=\204\"\312c\210\313c\210\314\211\207\f\314=\203<h\311U\203<\307\310!\210\315c\207\316\317\305\"\207\320	!\207" [vhdl-stutter-mode count last-input-event this-command last-command 1 vhdl-in-literal delete-char -1 32 " " ": " vhdl-electric-colon "= " insert-char 59 self-insert-command] 3 (#$ . 273346) "p"])
#@17 ',,' --> ' <= '
(defalias 'vhdl-electric-comma #[(count) "\203*	\303U\203*\304 \204*h\nU\203%\305\306!\210h\307=\204\"\310c\210\311c\207\312\313\303\"\207\314	!\207" [vhdl-stutter-mode count last-input-event 1 vhdl-in-literal delete-char -1 32 " " "<= " insert-char 44 self-insert-command] 3 (#$ . 273801) "p"])
#@17 '..' --> ' => '
(defalias 'vhdl-electric-period #[(count) "\203*	\303U\203*\304 \204*h\nU\203%\305\306!\210h\307=\204\"\310c\210\311c\207\312\313\303\"\207\314	!\207" [vhdl-stutter-mode count last-input-event 1 vhdl-in-literal delete-char -1 32 " " "=> " insert-char 46 self-insert-command] 3 (#$ . 274125) "p"])
#@17 '==' --> ' == '
(defalias 'vhdl-electric-equal #[(count) "\203*	\303U\203*\304 \204*h\nU\203%\305\306!\210h\307=\204\"\310c\210\311c\207\312\313\303\"\207\314	!\207" [vhdl-stutter-mode count last-input-event 1 vhdl-in-literal delete-char -1 32 " " "== " insert-char 61 self-insert-command] 3 (#$ . 274450) "p"])
#@65 Insert a pair of round parentheses, placing point between them.
(defalias 'vhdl-template-paired-parens #[nil "\300c\210\301u\207" ["()" -1] 1 (#$ . 274774) nil])
#@27 Insert alias declaration.
(defalias 'vhdl-template-alias #[nil "`\301\302!\210\303\304\305\306`%\2053\307c\210\303\310\311\312!\205\313\314Q\305\306#\204(\315\316!\210\301\317!\210\303\304\320\"\210\321 )\207" [start vhdl-insert-keyword "ALIAS " vhdl-template-field "name" nil t " : " "[type" vhdl-standard-p ams " or nature" "]" delete-char -3 " IS " ";" vhdl-comment-insert-inline] 6 (#$ . 274942) nil])
#@22 Insert architecture.
(defalias 'vhdl-template-architecture #[nil "\306 `\307\310\311!\210\312\313\307\314	`%\211\205S\310\315!\210\212\314\316 p\317\216\320!\210\321\322\307\314#-\203;\323\324!c\210\202?\312\325!\210\310\326!\210\327\330\331!?\205L\332\n\333>$+\207" [arch-name start margin case-fold-search #1=#:buffer #2=#:table current-indentation nil vhdl-insert-keyword "ARCHITECTURE " vhdl-template-field "name" t " OF " syntax-table ((byte-code "rq\210\302	!\210)\302\207" [#1# #2# set-syntax-table] 2)) set-syntax-table vhdl-re-search-backward "\\<entity \\(\\w+\\) is\\>" match-string 1 "entity name" " IS\n" vhdl-template-begin-end vhdl-standard-p 87 "ARCHITECTURE" (unit all) vhdl-mode-ext-syntax-table vhdl-insert-empty-lines] 6 (#$ . 275360) nil])
#@31 Insert array type definition.
(defalias 'vhdl-template-array #[(kind &optional secondary) "`\303\304!\210\305\306\307	?`%\204	\205*\303\310!\210\305\n\311=\203$\312\202%\313!\210\303\314!)\207" [start secondary kind vhdl-insert-keyword "ARRAY (" vhdl-template-field "range" nil ") OF " type "type" "nature" ";"] 6 (#$ . 276144) nil])
#@32 Insert an assertion statement.
(defalias 'vhdl-template-assert #[nil "`\302\303!\210	\203
\304c\210\305\306\307\310`%\205H	\203\311c\210`\302\312!\210\305\313\307\211\211\211\310&\2044`|\210`\302\314!\210\305\315\307\310#\204F`|\210\316c)\207" [start vhdl-conditions-in-parenthesis vhdl-insert-keyword "ASSERT " "(" vhdl-template-field "condition (negated)" nil t ")" " REPORT " "string expression" " SEVERITY " "[NOTE | WARNING | ERROR | FAILURE]" ";"] 7 (#$ . 276491) nil])
#@51 Insert an attribute declaration or specification.
(defalias 'vhdl-template-attribute #[nil "\300\301\302\303#\304=\203
\305 \207\306 \207" [vhdl-decision-query "attribute" "(d)eclaration or (s)pecification?" t 115 vhdl-template-attribute-spec vhdl-template-attribute-decl] 4 (#$ . 276986) nil])
#@34 Insert an attribute declaration.
(defalias 'vhdl-template-attribute-decl #[nil "`\301\302!\210\303\304\305\306`%\205\303\307\310\"\210\311 )\207" [start vhdl-insert-keyword "ATTRIBUTE " vhdl-template-field "name" " : " t "type" ";" vhdl-comment-insert-inline] 6 (#$ . 277288) nil])
#@36 Insert an attribute specification.
(defalias 'vhdl-template-attribute-spec #[nil "`\301\302!\210\303\304\305\306`%\205%\301\307!\210\303\310\311\"\210\303\312!\210\301\313!\210\303\314\315\")\207" [start vhdl-insert-keyword "ATTRIBUTE " vhdl-template-field "name" nil t " OF " "entity names | OTHERS | ALL" " : " "entity class" " IS " "expression" ";"] 6 (#$ . 277580) nil])
#@17 Insert a block.
(defalias 'vhdl-template-block #[nil "\303 `\304\305\306!\210	b\210\307\310\304\311	`\312\\%\211\205L\313v\210\313u\210\314c\210\307\315\304\311#\2033\316c\210\2027\317\320!\210\321\322!\204A\305\323!\210\324c\210\325\326\n#\210\327 +\207" [label start margin current-indentation nil vhdl-insert-keyword ": BLOCK " vhdl-template-field "label" t 8 1 "(" "[guard expression]" ")" delete-char -2 vhdl-standard-p 87 " IS" "\n" vhdl-template-begin-end "BLOCK" vhdl-comment-block] 7 (#$ . 277964) nil])
#@41 Insert a block configuration statement.
(defalias 'vhdl-template-block-configuration #[nil "\303 `\304\305!\210\306\307\310\311`%\205%\304\312!\210	j\210\304\313!\210\314\210	\n\\j*\207" [start margin vhdl-basic-offset current-indentation vhdl-insert-keyword "FOR " vhdl-template-field "block name" nil t "\n\n" "END FOR;" 0] 6 (#$ . 278492) nil])
#@27 Insert a break statement.
(defalias 'vhdl-template-break #[nil "\302\303\304!\210`\305c\210\303\306!\210\307\310\311\312#\203\307\313\314\"\210\202.`\315v\210`|\210\307\310\314\312#\203:\307\316!\210`\317c\210\202`|\210\320 \204X\303\321!\210\307\322\302\312#\203T`\202X`|\210\303\323!\210	\203c\324c\210\307\325\302\312#\203u	\203y\326c\210\202y`|\210\327c)\207" [position vhdl-conditions-in-parenthesis nil vhdl-insert-keyword "BREAK" " " "FOR " vhdl-template-field "[quantity name]" " USE " t "quantity name" " => " -1 "expression" ", " vhdl-sequential-statement-p " ON " "[sensitivity list]" " WHEN " "(" "[condition]" ")" ";"] 4 (#$ . 278851) nil])
#@26 Insert a case statement.
(defalias 'vhdl-template-case #[(&optional kind) "\306 `\307\204\310 \204\311\312!\204\313\202\314\f\315=\203(\311\316!\203/\317\320!\210\202J\317\321!\210	b\210\322\323\307\324#\211\204D\325\326!\210\327v\210\327u\210\322\330\307\324	`%\205\227\317\331\313=\203`\332\202a\333\334Q!\210\nj\210\317\335!\210\203u\331\261\210\336c\210\337y\210\n
\\j\210\317\340!\210`#\341c\210\n
\\j\210\317\342!\210#b)+\207" [label start margin kind vhdl-optional-labels vhdl-basic-offset current-indentation nil vhdl-sequential-statement-p vhdl-standard-p ams is use all 87 vhdl-insert-keyword "CASE " ": CASE " vhdl-template-field "[label]" t delete-char 2 1 "expression" " " "IS" "USE" "\n\n" "END CASE" ";" -1 "WHEN " " => ;\n" "WHEN OTHERS => null;" position] 7 (#$ . 279531) nil])
#@37 Insert a sequential case statement.
(defalias 'vhdl-template-case-is #[nil "\300\301!\207" [vhdl-template-case is] 2 (#$ . 280360) nil])
#@39 Insert a simultaneous case statement.
(defalias 'vhdl-template-case-use #[nil "\300\301!\207" [vhdl-template-case use] 2 (#$ . 280503) nil])
#@33 Insert a component declaration.
(defalias 'vhdl-template-component #[nil "\300 \207" [vhdl-template-component-decl] 1 (#$ . 280650) nil])
#@111 Insert a component configuration (uses `vhdl-template-configuration-spec'
since these are almost equivalent).
(defalias 'vhdl-template-component-conf #[nil "\302 \303\304!\205\305c\210	j\210\306\307!\210\310=\205\311*\207" [result margin current-indentation vhdl-template-configuration-spec t "\n" vhdl-insert-keyword "END FOR;" no-use 0] 3 (#$ . 280795) nil])
#@33 Insert a component declaration.
(defalias 'vhdl-template-component-decl #[nil "\305 `\306\211\307\310!\210\311\312\306\313\n`%\211\205\\\314\315!\204#\307\316!\210\317c\210j\210\307\320!\210\314\315!\2048\321	\261\210\322c\210i\323\210\f\\j\210\324\313\211\"\210\325c\210\f\\j\210\326\313!\210\327\330!\210u,\207" [end-column name start margin vhdl-basic-offset current-indentation nil vhdl-insert-keyword "COMPONENT " vhdl-template-field "name" t vhdl-standard-p 87 " IS" "\n\n" "END COMPONENT" " " ";" 0 vhdl-template-generic-list "\n" vhdl-template-port-list beginning-of-line 2] 6 (#$ . 281171) nil])
#@45 Insert a component instantiation statement.
(defalias 'vhdl-template-component-inst #[nil "\305 `\306\211\307\310\306\311\n`%\205\257\312c\210\313 \204\"\307\314!\210\202x\307\315\316\311#\211\206-\317\226\211\320\232\203[\307\321\322\306\211\211\211\323 &\210\307\324\325\"\210\307\326\306\311#\203T\327c\210\202x\330\331!\210\202x	\332\232\203t\307\321\322\306\211\211\211\323 &\210\307\333!\210\202x\307\314!\210\334c\210\f\\j\210`\335\336!\210\337\311\211#\203\226\334c\210\f\\j\210`\335\340!\210\337\311\211#\204\255\341 `|\210\330\331!\210\342c,\207" [position unit start margin vhdl-basic-offset current-indentation nil vhdl-template-field "instance label" t ": " vhdl-use-direct-instantiation "component name" "[COMPONENT | ENTITY | CONFIGURATION]" " " "" "ENTITY" "library name" "." vhdl-work-library "entity name" "(" "[architecture name]" ")" delete-char -1 "CONFIGURATION" "configuration name" "\n" vhdl-insert-keyword "GENERIC " vhdl-template-map "PORT " line-beginning-position ";"] 9 (#$ . 281797) nil])
#@41 Insert a conditional signal assignment.
(defalias 'vhdl-template-conditional-signal-asst #[nil "\305\306!\205d\307c\210i`\310\305\311!\210`\312\313!\210\203 \314c\210\305\315\310\316#\203S\203/\317c\210`\312\320!\210\321c\210\nj\210\305\322\310\316#\203S`\312\313!\210\203 \314c\210\202 `|\210\323c\210\f\205c\324	`\325#+\207" [position start margin vhdl-conditions-in-parenthesis vhdl-auto-align vhdl-template-field "target signal" " <= " nil "waveform" vhdl-insert-keyword " WHEN " "(" "[condition]" t ")" " ELSE" "\n" "[waveform]" ";" vhdl-align-region-groups 1] 4 (#$ . 282848) nil])
#@196 Insert a configuration specification if within an architecture,
a block or component configuration if within a configuration declaration,
a configuration declaration if not within a design unit.
(defalias 'vhdl-template-configuration #[nil "\304\305 p\306\216\307!\210\212\310\311\312\304#)\203%\313\314!\226\315\232\203%\316 \202N\212\310\317\312\304#)\203L\313\314!\226\320\232\203L\321\322\323\304#\324=\203G\325 \202N\326 \202N\327 ,\207" [case-fold-search #1=#:buffer #2=#:table vhdl-mode-ext-syntax-table t syntax-table ((byte-code "rq\210\302	!\210)\302\207" [#1# #2# set-syntax-table] 2)) set-syntax-table re-search-backward "^\\(architecture\\|end\\)\\>" nil match-string 1 "ARCHITECTURE" vhdl-template-configuration-spec "^\\(configuration\\|end\\)\\>" "CONFIGURATION" vhdl-decision-query "configuration" "(b)lock or (c)omponent configuration?" 99 vhdl-template-component-conf vhdl-template-block-configuration vhdl-template-configuration-decl] 4 (#$ . 283461) nil])
#@39 Insert a configuration specification.
(defalias 'vhdl-template-configuration-spec #[(&optional optional-use) "\306 `\307\211\310\311!\210\312\313\314\315\n`%\205\327\312\316\317\"\210\f\\j\210`\310\320!\210
\203=\312\321\322\315#\211\204=\n`|\210\323\202\327
\204F\312\324\322\"	\206K\325\226\211\326\232\203\266\312\327\330\307\211\211\211\331 &\210\312\332\333\"\210\312\334\307\315#\203r\335c\210\202v\336\337!\210\317c\210\f\340_\\j\210`\310\341!\210\342\315\211#\203\230\317c\210\f\340_\\j\210`\310\343!\210\342\315\211#\204\257\344 `|\210\336\337!\210\345c\210\315\202\327	\346\232\203\317\312\327\330\307\211\211\211\331 &\210\312\347\345\"\202\327\336\337!\210\345c\210\315,\207" [position aspect start margin vhdl-basic-offset optional-use current-indentation nil vhdl-insert-keyword "FOR " vhdl-template-field "instance names | OTHERS | ALL" " : " t "component name" "\n" "USE " "[ENTITY | CONFIGURATION | OPEN]" " " no-use "ENTITY | CONFIGURATION | OPEN" "" "ENTITY" "library name" "." vhdl-work-library "entity name" "(" "[architecture name]" ")" delete-char -1 2 "GENERIC " vhdl-template-map "PORT " line-beginning-position ";" "CONFIGURATION" "configuration name"] 9 (#$ . 284457) nil])
#@37 Insert a configuration declaration.
(defalias 'vhdl-template-configuration-decl #[nil "\306 `\307\211\211\211\310\311!\210\312\313\307\314\f`%\211\205\215\310\315!\210\212\314\316 p !\317\216\320\"!\210\321\322\307\314#\323\324!-\203N\n\325\232\204N\nc\210\202R\312\326!\210\310\327!\210#\330>\203`\331c\210
$\\j\210`\331c\210#\332>\203u\331c\210
j\210\310\333!\210\334\335!\204\206\310\311!\210	\336\261\210b.\207" [position name string entity-exists start margin current-indentation nil vhdl-insert-keyword "CONFIGURATION " vhdl-template-field "name" t " OF " syntax-table ((byte-code "rq\210\302	!\210)\302\207" [#1=#:buffer #2=#:table set-syntax-table] 2)) set-syntax-table vhdl-re-search-backward "\\<entity \\(\\w*\\) is\\>" match-string 1 "" "entity name" " IS\n" (unit all) "\n" (unit all) "END " vhdl-standard-p 87 ";" case-fold-search #1# #2# vhdl-mode-ext-syntax-table vhdl-insert-empty-lines vhdl-basic-offset] 6 (#$ . 285695) nil])
#@32 Insert a constant declaration.
(defalias 'vhdl-template-constant #[nil "`\303 \304\305!\210\306\307\310\311	`%\205E\312c\210\203\304\313!\210\306\314!\210\203.\315c\210\316 \202E`\317c\210\306\320\310\311#\204?\n`|\210\315c\210\316 )*\207" [in-arglist start position vhdl-in-argument-list-p vhdl-insert-keyword "CONSTANT " vhdl-template-field "name" nil t " : " "IN " "type" ";" vhdl-comment-insert-inline " := " "[initialization]"] 6 (#$ . 286676) nil])
#@17 Insert nothing.
(defalias 'vhdl-template-default #[nil "\300c\210\301 \210\302v\210\303\304!\210\304u\207" [" " unexpand-abbrev -1 vhdl-case-word 1] 2 (#$ . 287148) nil])
#@28 Insert nothing and indent.
(defalias 'vhdl-template-default-indent #[nil "\300c\210\301 \210\302v\210\303\304!\210\304u\210\305 \207" [" " unexpand-abbrev -1 vhdl-case-word 1 indent-according-to-mode] 2 (#$ . 287325) nil])
#@32 Insert a disconnect statement.
(defalias 'vhdl-template-disconnect #[nil "`\301\302!\210\303\304\305\306`%\205\303\307!\210\301\310!\210\303\311\312\")\207" [start vhdl-insert-keyword "DISCONNECT " vhdl-template-field "signal names | OTHERS | ALL" " : " t "type" " AFTER " "time expression" ";"] 6 (#$ . 287554) nil])
#@27 Insert an else statement.
(defalias 'vhdl-template-else #[nil "\306\307\310 p\311\216\312\f!\210\313\314!\210\212\315\316\306\307#)\203+\317\320!\226\321\232\203+\322c\2028\323 \210\324 \325c\210
\\j-\207" [margin case-fold-search #1=#:buffer #2=#:table vhdl-mode-ext-syntax-table vhdl-basic-offset nil t syntax-table ((byte-code "rq\210\302	!\210)\302\207" [#1# #2# set-syntax-table] 2)) set-syntax-table vhdl-insert-keyword "ELSE" vhdl-re-search-backward "\\(\\<when\\>\\|;\\)" match-string 1 "WHEN" " " indent-according-to-mode current-indentation "\n"] 4 (#$ . 287882) nil])
#@28 Insert an elsif statement.
(defalias 'vhdl-template-elsif #[nil "`\304\305\306!\210\307 \204\310\311!\205E\n\203\312c\210\313\314\304\315	`%\205E\n\203+\316c\210\317 \210\320 \305\321\307 \203<\322\202=\323\324Q!\210\\j*\207" [margin start vhdl-conditions-in-parenthesis vhdl-basic-offset nil vhdl-insert-keyword "ELSIF " vhdl-sequential-statement-p vhdl-standard-p ams "(" vhdl-template-field "condition" t ")" indent-according-to-mode current-indentation " " "THEN" "USE" "\n"] 6 (#$ . 288477) nil])
#@19 Insert an entity.
(defalias 'vhdl-template-entity #[nil "\306 `\307\211\310\311!\210\312\313\307\314\n`%\211\205w\310\315!\210j\210\310\316!\210\317\320!\204.\310\311!\210	\321\261\210i\322\210\f\\j\210
\323>\203F\324c\210\f\\j\210\325\314!\203Z
\326>\203Z\324c\210\324c\210\f\\j\210\327\314!\203q
\330>\203q\324c\210\331\332!\210u,\207" [end-column name start margin vhdl-basic-offset vhdl-insert-empty-lines current-indentation nil vhdl-insert-keyword "ENTITY " vhdl-template-field "name" t " IS\n\n" "END " vhdl-standard-p 87 ";" 0 (unit all) "\n" vhdl-template-generic-list (unit all) vhdl-template-port-list (unit all) beginning-of-line 2] 6 (#$ . 288999) nil])
#@27 Insert an exit statement.
(defalias 'vhdl-template-exit #[nil "`\303\304!\210\305\306\307\310`%\2037`\303\311!\210\n\203\312c\210\305\313\307\310#\203/\n\2033\314c\210\2023	`|\210)\202;\315\316!\210\317c)\207" [start position vhdl-conditions-in-parenthesis vhdl-insert-keyword "EXIT " vhdl-template-field "[loop label]" nil t " WHEN " "(" "[condition]" ")" delete-char -1 ";"] 6 (#$ . 289692) nil])
#@28 Insert a file declaration.
(defalias 'vhdl-template-file #[nil "`\301\302!\210\303\304\305\306`%\205L\307c\210\303\310!\210\311\312!\204-\301\313!\210\303\314\305\306#\204-\315\316!\210\301\317!\210\311\312!\203=\303\320\321\306#\210\303\322\305\211\211\211\306&\210\323c\210\324 )\207" [start vhdl-insert-keyword "FILE " vhdl-template-field "name" nil t " : " "type" vhdl-standard-p 87 " OPEN " "[READ_MODE | WRITE_MODE | APPEND_MODE]" delete-char -6 " IS " "[IN | OUT]" " " "filename-string" ";" vhdl-comment-insert-inline] 7 (#$ . 290107) nil])
#@290 Insert a block or component configuration if within a configuration
declaration, a configuration specification if within an architecture
declarative part (and not within a subprogram), a for-loop if within a
sequential statement part (subprogram or process), and a for-generate
otherwise.
(defalias 'vhdl-template-for #[nil "\304\305 p\306\216\307!\210\310 \203\311 \202X\212\312\313\314\304#)\203>\315\316!\226\317\232\203>\320\321\322\304#\323=\2039\324 \202X\325 \202X\212\312\326\314\304#)\203V\315\316!\226\327\232\203V\330 \202X\331 ,\207" [case-fold-search #1=#:buffer #2=#:table vhdl-mode-ext-syntax-table t syntax-table ((byte-code "rq\210\302	!\210)\302\207" [#1# #2# set-syntax-table] 2)) set-syntax-table vhdl-sequential-statement-p vhdl-template-for-loop re-search-backward "^\\(configuration\\|end\\)\\>" nil match-string 1 "CONFIGURATION" vhdl-decision-query "for" "(b)lock or (c)omponent configuration?" 99 vhdl-template-component-conf vhdl-template-block-configuration "^\\(architecture\\|entity\\|begin\\|end\\)\\>" "ARCHITECTURE" vhdl-template-configuration-spec vhdl-template-for-generate] 4 (#$ . 290669) nil])
#@24 Insert a for-generate.
(defalias 'vhdl-template-for-generate #[nil "\304 `\305\211\306\307!\210\310 \nb\210\311\312\305\313\n%\211\2052b\210\311\314!\210\306\315!\210\311\316!\210\317	\",\207" [position label start margin current-indentation nil vhdl-insert-keyword ": FOR " point-marker vhdl-template-field "label" t "loop variable" " IN " "range" vhdl-template-generate-body] 6 (#$ . 291823) nil])
#@20 Insert a for loop.
(defalias 'vhdl-template-for-loop #[nil "\306 `\307\211\f\310=\204\311\312!\210\2021\311\313!\210\nb\210\314\315\307\316#\211\204+\317\320!\210\321v\210\321u\210\314\322\307\316\n`%\211\205q\311\323!\210\314\324!\210\311\325!\210j\210\311\326!\210	\203]\327	\330\261\210\202i\330c\210
\203i\331\261\210\332y\210\\j,\207" [index label start margin vhdl-optional-labels vhdl-self-insert-comments current-indentation nil all vhdl-insert-keyword "FOR " ": FOR " vhdl-template-field "[label]" t delete-char 2 1 "loop variable" " IN " "range" " LOOP\n\n" "END LOOP" " " ";" "  -- " -1 vhdl-basic-offset] 7 (#$ . 292239) nil])
#@40 Insert a function declaration or body.
(defalias 'vhdl-template-function #[(&optional kind) "\306 `\307\310\311!\210\312\313\307\314	`%\211\205c\315\314!\210\203%\316	`\317#\210\307\210\320c\210\n\f\\j\210\310\321!\210\312\322!\210
\203B
\323=\202H\324\307\325\"\326=\203a\310\327!\210\330\331\332!?\205X\333\n#\210\334 \202c\335c+\207" [name start margin vhdl-auto-align vhdl-basic-offset kind current-indentation nil vhdl-insert-keyword "FUNCTION " vhdl-template-field "name" t vhdl-template-argument-list vhdl-align-region-groups 1 "\n" "RETURN " "type" body vhdl-decision-query "(d)eclaration or (b)ody?" 98 " IS\n" vhdl-template-begin-end vhdl-standard-p 87 "FUNCTION" vhdl-comment-block ";"] 6 (#$ . 292905) nil])
#@32 Insert a function declaration.
(defalias 'vhdl-template-function-decl #[nil "\300\301!\207" [vhdl-template-function decl] 2 (#$ . 293645) nil])
#@32 Insert a function declaration.
(defalias 'vhdl-template-function-body #[nil "\300\301!\207" [vhdl-template-function body] 2 (#$ . 293795) nil])
#@29 Insert a generation scheme.
(defalias 'vhdl-template-generate #[nil "\300\301\302\303#\304=\203
\305 \207\306 \207" [vhdl-decision-query nil "(f)or or (i)f?" t 105 vhdl-template-if-generate vhdl-template-for-generate] 4 (#$ . 293945) nil])
#@73 Insert generic declaration, or generic map in instantiation statements.
(defalias 'vhdl-template-generic #[nil "`\306\307 p\310\216\311\f!\210\212\312\313\314\306#)\203(\315\316!\226\317\232\203(\320\314!\202O\212\321 \2061\322\323!)\204A\324 \211@@)\325\232\203K\326\327!\210\330!\202O\320\314\306\"-\207" [start case-fold-search #1=#:buffer #2=#:table vhdl-mode-ext-syntax-table x t syntax-table ((byte-code "rq\210\302	!\210)\302\207" [#1# #2# set-syntax-table] 2)) set-syntax-table re-search-backward "^\\(entity\\|end\\)\\>" nil match-string 1 "ENTITY" vhdl-template-generic-list beginning-of-line looking-at "^\\s-*\\w+\\s-*:\\s-*\\w+" vhdl-get-syntactic-context statement-cont vhdl-insert-keyword "GENERIC " vhdl-template-map] 5 (#$ . 294192) nil])
#@45 Insert group or group template declaration.
(defalias 'vhdl-template-group #[nil "`\301\302\303\304#\305=\203\306 \202\307 )\207" [start vhdl-decision-query "group" "(d)eclaration or (t)emplate declaration?" t 116 vhdl-template-group-template vhdl-template-group-decl] 4 (#$ . 294968) nil])
#@27 Insert group declaration.
(defalias 'vhdl-template-group-decl #[nil "`\301\302!\210\303\304\305\306`%\205\303\307\310\"\210\303\311\312\"\210\313 )\207" [start vhdl-insert-keyword "GROUP " vhdl-template-field "name" " : " t "template name" " (" "constituent list" ");" vhdl-comment-insert-inline] 6 (#$ . 295270) nil])
#@36 Insert group template declaration.
(defalias 'vhdl-template-group-template #[nil "`\301\302!\210\303\304\305\306`%\205\301\307!\210\303\310\311\"\210\312 )\207" [start vhdl-insert-keyword "GROUP " vhdl-template-field "template name" nil t " IS (" "entity class list" ");" vhdl-comment-insert-inline] 6 (#$ . 295599) nil])
#@63 Insert a sequential if statement or an if-generate statement.
(defalias 'vhdl-template-if #[nil "\300 \203\301 \207\302\303!\203\304\305\306\307#\310=\203\311 \207\312 \207" [vhdl-sequential-statement-p vhdl-template-if-then vhdl-standard-p ams vhdl-decision-query "if" "(g)enerate or (u)se?" t 117 vhdl-template-if-use vhdl-template-if-generate] 4 (#$ . 295931) nil])
#@24 Insert an if-generate.
(defalias 'vhdl-template-if-generate #[nil "\305 `\306\211\307\310!\210\311 \nb\210\312\313\306\314\n%\211\2058b\210\f\203)\315c\210\312\316!\210\f\2034\317c\210\320	\",\207" [position label start margin vhdl-conditions-in-parenthesis current-indentation nil vhdl-insert-keyword ": IF " point-marker vhdl-template-field "label" t "(" "condition" ")" vhdl-template-generate-body] 6 (#$ . 296312) nil])
#@35 Insert a sequential if statement.
(defalias 'vhdl-template-if-then-use #[(kind) "\306 `\307\310=\203\311\312!\203\313\314!\210\2025\313\315!\210	b\210\316\317\307\320#\211\204/\321\322!\210\323v\210\323u\210\f\203<\324c\210\316\325\307\320	`%\205\205\f\203M\326c\210\313\327
\330=\203Y\331\202Z\332\333Q!\210\nj\210\313\334
\330=\203m\335\202n\332P!\210\203z\327\261\210\336c\210\337y\210\n \\j+\207" [label start margin vhdl-optional-labels vhdl-conditions-in-parenthesis kind current-indentation nil all vhdl-standard-p 87 vhdl-insert-keyword "IF " ": IF " vhdl-template-field "[label]" t delete-char 2 1 "(" "condition" ")" " " then "THEN" "USE" "\n\n" "END " "IF" ";" -1 vhdl-basic-offset] 7 (#$ . 296754) nil])
#@35 Insert a sequential if statement.
(defalias 'vhdl-template-if-then #[nil "\300\301!\207" [vhdl-template-if-then-use then] 2 (#$ . 297499) nil])
#@37 Insert a simultaneous if statement.
(defalias 'vhdl-template-if-use #[nil "\300\301!\207" [vhdl-template-if-then-use use] 2 (#$ . 297649) nil])
#@45 Insert a component instantiation statement.
(defalias 'vhdl-template-instance #[nil "\300 \207" [vhdl-template-component-inst] 1 (#$ . 297799) nil])
#@33 Insert a library specification.
(defalias 'vhdl-template-library #[nil "\304 `\305\211\306\307!\210\310\311\305\312\n`%\211\205J\313c\210\314\315	\"?\205J`\316c\210j\210\306\317!\210	c\210\306\320!\210\321u\210\310\322!\203E\323u\202J`\323\\|,\207" [end-pos name start margin current-indentation nil vhdl-insert-keyword "LIBRARY " vhdl-template-field "names" t ";" string-match "," "\n" "USE " "..ALL;" -5 "package name" 5] 6 (#$ . 297954) nil])
#@17 Insert a limit.
(defalias 'vhdl-template-limit #[nil "`\301\302!\210\303\304\305\306`%\205\303\307!\210\301\310!\210\303\311\312\")\207" [start vhdl-insert-keyword "LIMIT " vhdl-template-field "quantity names | OTHERS | ALL" " : " t "type" " WITH " "real expression" ";"] 6 (#$ . 298418) nil])
#@16 Insert a loop.
(defalias 'vhdl-template-loop #[nil "\301\302\303\304#\211\305=\203\306 \202\307=\203\310 \202\311 )\207" [char vhdl-decision-query nil "(w)hile, (f)or, or (b)are?" t 119 vhdl-template-while-loop 102 vhdl-template-for-loop vhdl-template-bare-loop] 5 (#$ . 298722) nil])
#@16 Insert a loop.
(defalias 'vhdl-template-bare-loop #[nil "\305 `\306\307=\204\310\311!\210\2020\310\312!\210	b\210\313\314\306\315#\211\204)\316\317!\210\320v\210\316\320!\210\321c\210\nj\210\310\322!\210\203E\323\324Q\202F\324c\210\325y\210\n\f\\j+\207" [label start margin vhdl-optional-labels vhdl-basic-offset current-indentation nil all vhdl-insert-keyword "LOOP " ": LOOP " vhdl-template-field "[label]" t delete-char 2 1 "\n\n" "END LOOP" " " ";" -1] 5 (#$ . 299023) nil])
#@51 Insert a map specification with association list.
(defalias 'vhdl-template-map #[(&optional start optional secondary) "\206`\306\211\307\310!\210\204E\311\f\205\312\313\f\205\314Q\315
?\206&\f
?\205,`%\2035\316\202\306\f\203A
\203A`|\210\306\202\306\203Oi\202[\317 \\\320c\210\nj\210\311\f\205a\312\321\f\205g\314Q\322
?\206o\f
?\205u`%\203\271\311\323\324\"\210`\320c\210\nj\210\311\325\322\316#\203\237\311\323\324\"\210`\320c\210\nj\210\202\207	`|\210\326\327!\210\315c\210\203\265\330`\331#\210\316\202\306\f\203\305
\203\305`|\210\306+\207" [start end-pos margin vhdl-association-list-with-formals optional secondary nil vhdl-insert-keyword "MAP (" vhdl-template-field "[" "association list" "]" ")" t current-indentation "\n" "formal" " => " "actual" "," "[formal]" delete-char -1 vhdl-align-region-groups 1 vhdl-argument-list-indent vhdl-basic-offset vhdl-auto-align] 6 (#$ . 299521) nil])
#@30 Actualize modification date.
(defalias 'vhdl-template-modify #[(&optional noerror) "\306\307 \310\211\211\311
!\210\312\313!\203?\313 \314\n@\nA\"\211\203?\n@\315\316!>\2038	B\317\315\310#\210\nA\211\204#\320\216\212eb\210\321\310\306#\203Z`\310\210`|\210\322 \202e?\205e\323\324\".\207" [overlay overlay-intangible-list overlay-all-list current-syntax-table case-fold-search vhdl-mode-ext-syntax-table t syntax-table nil set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) re-search-forward vhdl-template-insert-date error "ERROR:  Modification date prefix string \"%s\" not found" vhdl-modify-date-prefix-string noerror] 6 (#$ . 300471) nil])
#@51 Call `vhdl-template-modify' with NOERROR non-nil.
(defalias 'vhdl-template-modify-noerror #[nil "\300\301!\207" [vhdl-template-modify t] 2 (#$ . 301388)])
#@30 Insert a nature declaration.
(defalias 'vhdl-template-nature #[nil "`\305\211\211\306\307!\210\310\311\305\312`%\211\205\212\306\313!\210\310\314!\206#\315\226\211\315\232\2031\316c\210\202s\f\317\232\203F`\320v\210`|\210\321\322\312\"\210\202s\f\323\232\203_\324 `\320v\210`|\210\325\322\n\312#\210\202s\306\326!\210\310\327!\210\306\330!\210\310\331!\210\306\332!\210	\203\200\324 	b\210\305\210\333 \210\205\211b),\207" [end-pos mid-pos name start definition nil vhdl-insert-keyword "NATURE " vhdl-template-field "name" t " IS " "across type | ARRAY | RECORD" "" ";" "ARRAY" -1 vhdl-template-array nature "RECORD" point-marker vhdl-template-record " ACROSS " "through type" " THROUGH " "reference name" " REFERENCE;" vhdl-comment-insert-inline] 7 (#$ . 301549) nil])
#@26 Insert a next statement.
(defalias 'vhdl-template-next #[nil "`\303\304!\210\305\306\307\310`%\2037`\303\311!\210\n\203\312c\210\305\313\307\310#\203/\n\2033\314c\210\2023	`|\210)\202;\315\316!\210\317c)\207" [start position vhdl-conditions-in-parenthesis vhdl-insert-keyword "NEXT " vhdl-template-field "[loop label]" nil t " WHEN " "(" "[condition]" ")" delete-char -1 ";"] 6 (#$ . 302347) nil])
#@29 Insert an others aggregate.
(defalias 'vhdl-template-others #[nil "`h\302U\204\f	\204&	\204\303c\210\304\305!\210\306\307\310\311`%\205)\312c\202)\304\313!)\207" [start vhdl-template-invoked-by-hook 40 "(" vhdl-insert-keyword "OTHERS => '" vhdl-template-field "value" nil t "')" "OTHERS "] 6 (#$ . 302761) nil])
#@41 Insert a package specification or body.
(defalias 'vhdl-template-package #[(&optional kind) "\306 `\307\211\211\310\311!\210
\203
\301=\202\312\307\313\"\314=\211\203J\310\315!\210\212\316!\317 p\"#\320\216\321$!\210\322\323\307\316#-\203J\324\325!\211c\210\n\204Z\326\327\307\316`%\211\205\237\310\330!\210%\331>\203h\332c\210\f&\\j\210`\332c\210%\333>\203}\332c\210\fj\210\310\334!\210\335\336!\204\224\310\311	\205\221\315P!\210\n\206\231\337\340\261\210b-\207" [position body name start margin kind current-indentation nil vhdl-insert-keyword "PACKAGE " vhdl-decision-query "(d)eclaration or (b)ody?" 98 "BODY " t syntax-table ((byte-code "rq\210\302	!\210)\302\207" [#1=#:buffer #2=#:table set-syntax-table] 2)) set-syntax-table vhdl-re-search-backward "\\<package \\(\\w+\\) is\\>" match-string 1 vhdl-template-field "name" " IS\n" (unit all) "\n" (unit all) "END " vhdl-standard-p 87 "" ";" case-fold-search #1# #2# vhdl-mode-ext-syntax-table vhdl-insert-empty-lines vhdl-basic-offset] 7 (#$ . 303087) nil])
#@33 Insert a package specification.
(defalias 'vhdl-template-package-decl #[nil "\300\301!\207" [vhdl-template-package decl] 2 (#$ . 304141) nil])
#@24 Insert a package body.
(defalias 'vhdl-template-package-body #[nil "\300\301!\207" [vhdl-template-package body] 2 (#$ . 304290) nil])
#@69 Insert a port declaration, or port map in instantiation statements.
(defalias 'vhdl-template-port #[nil "`\306\307 p\310\216\311\f!\210\212\312\313\314\306#)\203(\315\316!\226\317\232\203(\320\314!\202N\212\321 \2061\322\323!)\204A\324 \211@@)\325\232\203K\326\327!\210\330!\202N\320\314!-\207" [start case-fold-search #1=#:buffer #2=#:table vhdl-mode-ext-syntax-table x t syntax-table ((byte-code "rq\210\302	!\210)\302\207" [#1# #2# set-syntax-table] 2)) set-syntax-table re-search-backward "^\\(entity\\|end\\)\\>" nil match-string 1 "ENTITY" vhdl-template-port-list beginning-of-line looking-at "^\\s-*\\w+\\s-*:\\s-*\\w+" vhdl-get-syntactic-context statement-cont vhdl-insert-keyword "PORT " vhdl-template-map] 5 (#$ . 304430) nil])
#@22 Insert a procedural.
(defalias 'vhdl-template-procedural #[nil "\305 `\306\307\310\311!\210\f\312>\2030\nb\210\313c\210\nb\210\314\315\307\306#\211\204*\316\317!\210\320v\210\320u\210\321\322!\204:\310\323!\210\324c\210\325\326#\210\327 ,\207" [label case-fold-search start margin vhdl-optional-labels current-indentation t nil vhdl-insert-keyword "PROCEDURAL " (process all) ": " vhdl-template-field "[label]" delete-char 2 1 vhdl-standard-p 87 "IS" "\n" vhdl-template-begin-end "PROCEDURAL" vhdl-comment-block] 5 (#$ . 305188) nil])
#@41 Insert a procedure declaration or body.
(defalias 'vhdl-template-procedure #[(&optional kind) "\305 `\306\307\310!\210\311\312\306\313	`%\211\205b\314 \210\203$\315=\202*\316\306\317\"\320=\203S\307\321!\210\f\203;\322	`\323#\210\306\210\324c\210\325\326\327!?\205J\330\n#\210\331 \202b\332c\210\f\203`\322	`\323#\210\306+\207" [name start margin kind vhdl-auto-align current-indentation nil vhdl-insert-keyword "PROCEDURE " vhdl-template-field "name" t vhdl-template-argument-list body vhdl-decision-query "(d)eclaration or (b)ody?" 98 " IS" vhdl-align-region-groups 1 "\n" vhdl-template-begin-end vhdl-standard-p 87 "PROCEDURE" vhdl-comment-block ";"] 6 (#$ . 305739) nil])
#@33 Insert a procedure declaration.
(defalias 'vhdl-template-procedure-decl #[nil "\300\301!\207" [vhdl-template-procedure decl] 2 (#$ . 306438) nil])
#@26 Insert a procedure body.
(defalias 'vhdl-template-procedure-body #[nil "\300\301!\207" [vhdl-template-procedure body] 2 (#$ . 306591) nil])
#@19 Insert a process.
(defalias 'vhdl-template-process #[(&optional kind) "\306 `\307\211\211\211\211\211@ABCD\203#D\305=\202*\310\311\312\313#\314=\315\316!\210E\317>\203VBb\210\320c\210Bb\210\321\322\307\313#\211@\204P\323\324!\210\325v\210\325u\210\326c\210
\204p\321\327\330\313#\211\204\305\331\323\332!\210\202\305F\331\232\204\200Fc\210F\206\207\321\333!\206\207\334A\335=\203\240\310\331\336\313#\337=\203\235\340\202\236\341AA\340=\203\302\342c\210G\331\232\204\272Gc\210G\206\301\321\343!\206\301\344\330c\210\345\346!\204\317\315\347!\210\350c\210\351\352@C#\210
\203\345\353\nA#H\205\331
\354 \313\355 \307\211\211IJKLM\356N!\210\357\360!\203?
\360 K\361K@KA\"\211K\203?
K@I\362\363I!>\2036
IJBJ\364I\362\307#\210KA\211K\204
\365\216\366\367\307\313#\203\325
\366\370\307\313#\203\325
\371\210o\203a
\350c\210\372y\210\202d
\350c\210Cj\210\373c\210\321\374\307\313#\204y
\375 \210\202\325
\350c\210Cj\210\376c\210
\203\213
\377\202\216
\201O\350\261\210Cj\210\201Pc\210
\204\245
\fc\210\202\301
\342\261\210\n\203\263
\n\342\261\210\321\201Q\307\313#\204\301
\323\332!\210\350c\210Cj\210\201Rc\210\321\201Q\307\313#\210.	b.	\207" [vhdl-reset-kind final-pos reset clock input-signals seq current-indentation nil vhdl-decision-query "process" "(c)ombinational or (s)equential?" t 115 vhdl-insert-keyword "PROCESS " (process all) ": " vhdl-template-field "[label]" delete-char 2 1 "(" "[sensitivity list]" ")" "" -2 "clock name" "<clock>" query "(a)synchronous or (s)ynchronous reset?" 97 async sync ", " "reset name" "<reset>" vhdl-standard-p 87 " IS" "\n" vhdl-template-begin-end "PROCESS" vhdl-template-seq-process point-marker syntax-table set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) vhdl-re-search-backward "\\<begin\\>" "\\<process\\>" 0 -1 "-- purpose: " "[description]" vhdl-line-kill-entire "-- type   : " "sequential" label reset-kind start margin kind vhdl-optional-labels vhdl-clock-name vhdl-reset-name vhdl-prompt-for-comments overlay overlay-intangible-list overlay-all-list current-syntax-table case-fold-search vhdl-mode-ext-syntax-table "combinational" "-- inputs : " "[signal names]" "-- outputs: "] 10 (#$ . 306737) nil])
#@33 Insert a combinational process.
(defalias 'vhdl-template-process-comb #[nil "\300\301!\207" [vhdl-template-process comb] 2 (#$ . 309227) nil])
#@30 Insert a sequential process.
(defalias 'vhdl-template-process-seq #[nil "\300\301!\207" [vhdl-template-process seq] 2 (#$ . 309376) nil])
#@32 Insert a quantity declaration.
(defalias 'vhdl-template-quantity #[nil "\302 \203)`\303\304!\210\305\306\307\310`%\205'\311c\210\305\312\313\310#\210\305\314!\210\315c\210\316 )\207\317\320\321\310#\211\322=\203:\323 \202T	\324=\203E\325 \202T	\326=\203P\327 \202T\330``\")\207" [start char vhdl-in-argument-list-p vhdl-insert-keyword "QUANTITY " vhdl-template-field "names" nil t " : " "[IN | OUT]" " " "type" ";" vhdl-comment-insert-inline vhdl-decision-query "quantity" "(f)ree, (b)ranch, or (s)ource quantity?" 102 vhdl-template-quantity-free 98 vhdl-template-quantity-branch 115 vhdl-template-quantity-source vhdl-template-undo] 7 (#$ . 309520) nil])
#@37 Insert a free quantity declaration.
(defalias 'vhdl-template-quantity-free #[nil "\301\302!\210\303\304!\210\305c\210\303\306!\210`\307c\210\303\310\311\312#\204 `|\210\313c\210\314 )\207" [position vhdl-insert-keyword "QUANTITY " vhdl-template-field "names" " : " "type" " := " "[initialization]" nil t ";" vhdl-comment-insert-inline] 4 (#$ . 310193) nil])
#@39 Insert a branch quantity declaration.
(defalias 'vhdl-template-quantity-branch #[nil "\301\302\303!\210\304\305\306\307#\203\302\310!\210\304\311\306\307#\203\302\312!\210\304\313!\210`\302\314!\210\304\315\301\307#\2044`|\210\316c\210\317 )\207" [position nil vhdl-insert-keyword "QUANTITY " vhdl-template-field "[across names]" " " t "ACROSS " "[through names]" "THROUGH " "plus terminal name" " TO " "[minus terminal name]" ";" vhdl-comment-insert-inline] 4 (#$ . 310560) nil])
#@39 Insert a source quantity declaration.
(defalias 'vhdl-template-quantity-source #[nil "\300\301!\210\302\303!\210\304c\210\302\305\306\"\210\307\310\311\"\312=\203$\300\313!\210\302\314!\210\2021\300\315!\210\302\316\317\"\210\302\320!\210\321c\210\322 \207" [vhdl-insert-keyword "QUANTITY " vhdl-template-field "names" " : " "type" " " vhdl-decision-query nil "(s)pectrum or (n)oise?" 110 "NOISE " "power expression" "SPECTRUM " "magnitude expression" ", " "phase expression" ";" vhdl-comment-insert-inline] 3 (#$ . 311055) nil])
#@35 Insert a record type declaration.
(defalias 'vhdl-template-record #[(kind &optional name secondary) "i`\306\307\310!\210\n\\j\210\311\312\313\f?	`%\204\f\205w\204*\311\314\313\306#\203M\315c\210\311
\316=\2038\317\2029\320\321\"\210\322 \210\323c\210\n\\j\210\313\211\202\324 `|\210\nj\210\307\325!\210\326\327!\204j\203j\330\261\210\321c\210\205w\331	`\332#+\207" [first start margin vhdl-basic-offset secondary kind t vhdl-insert-keyword "RECORD\n" vhdl-template-field "element names" nil "[element names]" " : " type "type" "nature" ";" vhdl-comment-insert-inline "\n" line-beginning-position "END RECORD" vhdl-standard-p 87 " " vhdl-align-region-groups 1 name vhdl-auto-align] 7 (#$ . 311593) nil])
#@28 Insert a report statement.
(defalias 'vhdl-template-report #[nil "`\301\302!\210\303\304\305\306`\306&\307\232\203\310\311!\202.`\301\312!\210\303\313\305\306#\204,`|\210\314c)\207" [start vhdl-insert-keyword "REPORT " vhdl-template-field "string expression" nil t "\"\"" delete-char -2 " SEVERITY " "[NOTE | WARNING | ERROR | FAILURE]" ";"] 7 (#$ . 312328) nil])
#@28 Insert a return statement.
(defalias 'vhdl-template-return #[nil "`\301\302!\210\303\304\305\306`%\204\307\310!\210\311c)\207" [start vhdl-insert-keyword "RETURN " vhdl-template-field "[expression]" nil t delete-char -1 ";"] 6 (#$ . 312707) nil])
#@38 Insert a selected signal assignment.
(defalias 'vhdl-template-selected-signal-asst #[nil "\306 `\307`\310\311!\210b\210)\310\312!\210\313\314\315\307	`\316\\%\205\225\317v\210\320\317!\210\321c\210\n\f\\j\210\313\322\323\"\210\321c\210\n\f\\j\210\313\324!\210\310\325!\210\313\326\327\"\210\321c\210\n\f\\j\210\203~\313\330\315\307#\203~\310\325!\210\313\331\327\307#\211\203w\321c\210\n\f\\j\210\202R\310\332!\210\202R\203\211\333 \210\320\334!\210\335c\210
\205\225\336	`\317#+\207" [choices start margin position vhdl-basic-offset vhdl-auto-align current-indentation t vhdl-insert-keyword " SELECT " "WITH " vhdl-template-field "selector expression" nil 7 1 delete-char "\n" "target signal" " <= " "waveform" " WHEN " "choices" "," "[waveform]" "[choices]" "OTHERS" fixup-whitespace -2 ";" vhdl-align-region-groups] 7 (#$ . 312964) nil])
#@30 Insert a signal declaration.
(defalias 'vhdl-template-signal #[nil "`\303 \304\305!\210\306\307\310\311	`%\205G\312c\210\203 \306\313\314\311#\210\306\315!\210\2030\316c\210\317 \202G`\320c\210\306\321\310\311#\204A\n`|\210\316c\210\317 )*\207" [in-arglist start position vhdl-in-argument-list-p vhdl-insert-keyword "SIGNAL " vhdl-template-field "names" nil t " : " "[IN | OUT | INOUT]" " " "type" ";" vhdl-comment-insert-inline " := " "[initialization]"] 6 (#$ . 313827) nil])
#@33 Insert a subnature declaration.
(defalias 'vhdl-template-subnature #[nil "`\302\303\304!\210\305\306\302\307	`%\205_\303\310!\210\305\311\312\"\210\305\313\302\307#\203)\314c\210\202-\315\316!\210`\303\317!\210\305\320\302\307\302\211\307&\321\232\203H`|\210\202Z\303\322!\210\305\323\302\211\211\211\307&\210\303\324!\210\325c\210\326 *\207" [position start nil vhdl-insert-keyword "SUBNATURE " vhdl-template-field "name" t " IS " "nature" " (" "[index range]" ")" delete-char -2 " TOLERANCE " "[string expression]" "\"\"" " ACROSS " "string expression" " THROUGH" ";" vhdl-comment-insert-inline] 7 (#$ . 314321) nil])
#@27 Insert a subprogram body.
(defalias 'vhdl-template-subprogram-body #[nil "\300\301\302\303#\304=\203
\305 \207\306 \207" [vhdl-decision-query nil "(p)rocedure or (f)unction?" t 102 vhdl-template-function-body vhdl-template-procedure-body] 4 (#$ . 314958) nil])
#@34 Insert a subprogram declaration.
(defalias 'vhdl-template-subprogram-decl #[nil "\300\301\302\303#\304=\203
\305 \207\306 \207" [vhdl-decision-query nil "(p)rocedure or (f)unction?" t 102 vhdl-template-function-decl vhdl-template-procedure-decl] 4 (#$ . 315226) nil])
#@31 Insert a subtype declaration.
(defalias 'vhdl-template-subtype #[nil "`\301\302!\210\303\304\305\306`%\205*\301\307!\210\303\310\311\"\210\303\312\305\306#\204%\313\314!\210\315c\210\316 )\207" [start vhdl-insert-keyword "SUBTYPE " vhdl-template-field "name" nil t " IS " "type" " " "[RANGE value range | ( index range )]" delete-char -1 ";" vhdl-comment-insert-inline] 6 (#$ . 315501) nil])
#@32 Insert a terminal declaration.
(defalias 'vhdl-template-terminal #[nil "`\301\302!\210\303\304\305\306`%\205\307c\210\303\310!\210\311c\210\312 )\207" [start vhdl-insert-keyword "TERMINAL " vhdl-template-field "names" nil t " : " "nature" ";" vhdl-comment-insert-inline] 6 (#$ . 315903) nil])
#@28 Insert a type declaration.
(defalias 'vhdl-template-type #[nil "`\305\211\211\306\307!\210\310\311\305\312`%\211\205\242\306\313!\210\310\314\305\312#\206%\315\226\211\315\232\2037\316\317!\210\320c\210\202\213\f\321\232\203L`\322v\210`|\210\323\324\312\"\210\202\213\f\325\232\203e\326 `\322v\210`|\210\327\324\n\312#\210\202\213\f\330\232\203v\331c\210\310\332\320\"\210\202\213\f\333\232\203\210\306\334!\210\310\332\320\"\210\202\213\320c\210	\203\230\326 	b\210\305\210\335 \210\205\241b),\207" [end-pos mid-pos name start definition nil vhdl-insert-keyword "TYPE " vhdl-template-field "name" t " IS " "[scalar type | ARRAY | RECORD | ACCESS | FILE]" "" delete-char -4 ";" "ARRAY" -1 vhdl-template-array type "RECORD" point-marker vhdl-template-record "ACCESS" " " "type" "FILE" " OF " vhdl-comment-insert-inline] 7 (#$ . 316206) nil])
#@22 Insert a use clause.
(defalias 'vhdl-template-use #[nil "`\305\306 p\307\216\310\f!\210\311\312!\210\212\313 \210\314\315!)\205:\311\316!\210\317u\210\320\321\322\305`\323\\%\205:\324u\210\320\325!\210\326u-\207" [start case-fold-search #1=#:buffer #2=#:table vhdl-mode-ext-syntax-table t syntax-table ((byte-code "rq\210\302	!\210)\302\207" [#1# #2# set-syntax-table] 2)) set-syntax-table vhdl-insert-keyword "USE " beginning-of-line looking-at "^\\s-*use\\>" "..ALL;" -6 vhdl-template-field "library name" nil 6 1 "package name" 5] 7 (#$ . 317079) nil])
#@32 Insert a variable declaration.
(defalias 'vhdl-template-variable #[nil "`\306 \307\310 \311\211\211(\312)!\210\313\314!\203F\314 \315\f@\fA\"\211\203F\f@\316\317\n!>\203?\nB\320\n\316\311#\210\fA\211\204*\321\216\212\322 \210\323\324!)\204^\212\325v\210\323\326!)\203e\327\330!\210\202v\331\332!\203r\333\334!\210\202v\327\335!\210.\336\337\311\307	`%\205\270\340c\210\203\217\336\341\342\307#\210\336\343!\210\203\237\344c\210\345 \202\270`*\346c\210\336\347\311\307#\204\262*`|\210\344c\210\345 )*\207" [in-arglist start overlay overlay-intangible-list overlay-all-list current-syntax-table vhdl-in-argument-list-p t syntax-table nil set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) vhdl-beginning-of-block looking-at "\\s-*\\(\\w+\\s-*:\\s-*\\)?\\<\\(\\<function\\|procedure\\|process\\|procedural\\)\\>" -1 "\\<shared\\>" vhdl-insert-keyword "VARIABLE " vhdl-standard-p 87 error "ERROR:  Not within sequential block" "SHARED VARIABLE " vhdl-template-field "names" " : " "[IN | OUT | INOUT]" " " "type" ";" vhdl-comment-insert-inline " := " "[initialization]" case-fold-search vhdl-mode-ext-syntax-table position] 7 (#$ . 317649) nil])
#@26 Insert a wait statement.
(defalias 'vhdl-template-wait #[nil "\300\301!\210\302\303\304\305#\204\306\307!\210\310c\207" [vhdl-insert-keyword "WAIT " vhdl-template-field "[ON sensitivity list] [UNTIL condition] [FOR time expression]" nil t delete-char -1 ";"] 4 (#$ . 319068) nil])
#@46 Indent correctly if within a case statement.
(defalias 'vhdl-template-when #[nil "`\306\307\310 \306\211\211\311!\210\312\313!\203E\313 \314\f@\fA\"\211\203E\f@\315\316\n!>\203>\nB\317\n\315\306#\210\fA\211\204)\320\216i\321 U\203n\322\323\306\307#\203n\324\325!\203n\321 	b\210\326 \210\\j\210\202q	b\210.\327\330!*\207" [margin position overlay overlay-intangible-list overlay-all-list current-syntax-table nil t syntax-table set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) current-indentation vhdl-re-search-forward "\\<end\\>" looking-at "\\s-*\\<case\\>" delete-horizontal-space vhdl-insert-keyword "WHEN " case-fold-search vhdl-mode-ext-syntax-table vhdl-basic-offset] 6 (#$ . 319357) nil])
#@22 Insert a while loop.
(defalias 'vhdl-template-while-loop #[nil "\306 `\307\310=\204\311\312!\210\202/\311\313!\210	b\210\314\315\307\316#\211\204)\317\320!\210\321v\210\321u\210\f\2036\322c\210\314\323\307\316	`%\205g\f\203G\324c\210\311\325!\210j\210\311\326!\210\n\203]\327\n\330Q\202^\330c\210\331y\210
\\j+\207" [margin start label vhdl-optional-labels vhdl-conditions-in-parenthesis vhdl-basic-offset current-indentation nil all vhdl-insert-keyword "WHILE " ": WHILE " vhdl-template-field "[label]" t delete-char 2 1 "(" "condition" ")" " LOOP\n\n" "END LOOP" " " ";" -1] 7 (#$ . 320331) nil])
#@60 Insert a with statement (i.e. selected signal assignment).
(defalias 'vhdl-template-with #[nil "\304\305 p\306\216\307!\210\212\310\311!)\203\"\312\313!\314\232\203\"\315 \202%\316\317!,\207" [case-fold-search #1=#:buffer #2=#:table vhdl-mode-ext-syntax-table t syntax-table ((byte-code "rq\210\302	!\210)\302\207" [#1# #2# set-syntax-table] 2)) set-syntax-table vhdl-re-search-backward "\\(\\<limit\\>\\|;\\)" match-string 1 ";" vhdl-template-selected-signal-asst vhdl-insert-keyword "WITH "] 2 (#$ . 320952) nil])
#@56 Insert a wait statement for rising/falling clock edge.
(defalias 'vhdl-template-clocked-wait #[nil "`\306\307\310!\210\n\311\232\204\nc\210\n\206\312\313\306\314	`%\211\205F\315c\210\307\316!\210c\210\317\2034\f\2025
\320\261\210\321\203B\322\202C\323\324P!*\207" [clock start vhdl-clock-name vhdl-clock-rising-edge vhdl-one-string vhdl-zero-string nil vhdl-insert-keyword "WAIT UNTIL " "" vhdl-template-field "clock name" t "'event" " AND " " = " ";" vhdl-comment-insert-inline "rising" "falling" " clock edge"] 6 (#$ . 321482) nil])
#@57 Insert a template for the body of a sequential process.
(defalias 'vhdl-template-seq-process #[(clock reset reset-kind) "\306 \307\310\311!\210\n\203\312c\210\313=\203\\\f\314
\203!&\202#'\261\210\n\203-\315c\210\310\316!\210\317\320
\203;\321\202<\322\315Q!\210\323c\210	(\\j\210`\323c\210	j\210\310\324!\210\n\203\\\312c\210)\325=\203w*\203l\326\202m\327\330+\315\261\210\202\223+\331\261\210\310\332!\210+\314*\203\216&\202\220'\261\210\n\203\232\315c\210\310\316!\210\317*\203\250\326\202\251\327\333P!\210\323c\210	(\\j\210\334=\203:
\310\311!\210\n\203\307\312c\210,\335\232\204\327,c\210,\206\336\336\337!\206\336\340\314
\203\351&\202\353'\261\210\n\203\365\315c\210\310\316!\210\317\341
\203
\321\202
\322\315Q!\210\323c\210	(\342_\\j\210`\323c\210	(\\j\210\310\343!\210\323c\210	(\342_\\j\210\323c\210	(\\j\210\310\344!\210\345=\203B
`\323c\210	j\210\310\344!\210b\210\f*\207" [position margin vhdl-conditions-in-parenthesis reset-kind reset vhdl-reset-active-high current-indentation nil vhdl-insert-keyword "IF " "(" async " = " ")" " THEN" vhdl-comment-insert-inline "asynchronous reset (active " "high" "low" "\n" "ELSIF " function "rising" "falling" "_edge(" "'event" " AND " " clock edge" sync "" vhdl-template-field "reset name" "<reset>" "synchronous reset (active " 2 "ELSE" "END IF;" none vhdl-one-string vhdl-zero-string vhdl-basic-offset vhdl-clock-edge-condition vhdl-clock-rising-edge clock vhdl-reset-name] 4 (#$ . 322039)])
#@101 Insert specification of a standard package.  Include a library
specification, if not already there.
(defalias 'vhdl-template-standard-package #[(library package) "\306 	\307\232\204I\212\310\311 p\312\216\313
!\210o?\205*\314\315	\316Q\317\310#\205*\320\321!-\204I	\227\322\232\204I\323\324!\210	\325\261\210\203I\326c\210j\210\205\\\323\327!\210	\330\261\210\323\331!)\207" [margin library case-fold-search #1=#:buffer #2=#:table vhdl-mode-ext-syntax-table current-indentation "std" t syntax-table ((byte-code "rq\210\302	!\210)\302\207" [#1# #2# set-syntax-table] 2)) set-syntax-table re-search-backward "^\\s-*\\(\\(library\\)\\s-+\\(\\w+\\s-*,\\s-*\\)*" "\\|end\\)\\>" nil match-string 2 "work" vhdl-insert-keyword "LIBRARY " ";" "\n" "USE " "." ".ALL;" package] 4 (#$ . 323560)])
#@48 Insert specification of `numeric_bit' package.
(defalias 'vhdl-template-package-numeric-bit #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "numeric_bit"] 3 (#$ . 324372) nil])
#@48 Insert specification of `numeric_std' package.
(defalias 'vhdl-template-package-numeric-std #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "numeric_std"] 3 (#$ . 324573) nil])
#@51 Insert specification of `std_logic_1164' package.
(defalias 'vhdl-template-package-std-logic-1164 #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "std_logic_1164"] 3 (#$ . 324774) nil])
#@52 Insert specification of `std_logic_arith' package.
(defalias 'vhdl-template-package-std-logic-arith #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "std_logic_arith"] 3 (#$ . 324984) nil])
#@51 Insert specification of `std_logic_misc' package.
(defalias 'vhdl-template-package-std-logic-misc #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "std_logic_misc"] 3 (#$ . 325197) nil])
#@53 Insert specification of `std_logic_signed' package.
(defalias 'vhdl-template-package-std-logic-signed #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "std_logic_signed"] 3 (#$ . 325407) nil])
#@53 Insert specification of `std_logic_textio' package.
(defalias 'vhdl-template-package-std-logic-textio #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "std_logic_textio"] 3 (#$ . 325623) nil])
#@55 Insert specification of `std_logic_unsigned' package.
(defalias 'vhdl-template-package-std-logic-unsigned #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "std_logic_unsigned"] 3 (#$ . 325839) nil])
#@43 Insert specification of `textio' package.
(defalias 'vhdl-template-package-textio #[nil "\300\301\302\"\207" [vhdl-template-standard-package "std" "textio"] 3 (#$ . 326061) nil])
#@58 Insert specification of `fundamental_constants' package.
(defalias 'vhdl-template-package-fundamental-constants #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "fundamental_constants"] 3 (#$ . 326246) nil])
#@55 Insert specification of `material_constants' package.
(defalias 'vhdl-template-package-material-constants #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "material_constants"] 3 (#$ . 326477) nil])
#@51 Insert specification of `energy_systems' package.
(defalias 'vhdl-template-package-energy-systems #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "energy_systems"] 3 (#$ . 326699) nil])
#@55 Insert specification of `electrical_systems' package.
(defalias 'vhdl-template-package-electrical-systems #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "electrical_systems"] 3 (#$ . 326909) nil])
#@55 Insert specification of `mechanical_systems' package.
(defalias 'vhdl-template-package-mechanical-systems #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "mechanical_systems"] 3 (#$ . 327131) nil])
#@52 Insert specification of `radiant_systems' package.
(defalias 'vhdl-template-package-radiant-systems #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "radiant_systems"] 3 (#$ . 327353) nil])
#@52 Insert specification of `thermal_systems' package.
(defalias 'vhdl-template-package-thermal-systems #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "thermal_systems"] 3 (#$ . 327566) nil])
#@52 Insert specification of `fluidic_systems' package.
(defalias 'vhdl-template-package-fluidic-systems #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "fluidic_systems"] 3 (#$ . 327779) nil])
#@49 Insert specification of `math_complex' package.
(defalias 'vhdl-template-package-math-complex #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "math_complex"] 3 (#$ . 327992) nil])
#@46 Insert specification of `math_real' package.
(defalias 'vhdl-template-package-math-real #[nil "\300\301\302\"\207" [vhdl-template-standard-package "ieee" "math_real"] 3 (#$ . 328196) nil])
#@19 Insert directive.
(defalias 'vhdl-template-directive #[(directive) "\301 iU\204
\302 \210\303c\210\304\261\207" [directive current-indentation delete-horizontal-space "  " "-- pragma "] 2 (#$ . 328391)])
#@34 Insert directive 'translate_on'.
(defalias 'vhdl-template-directive-translate-on #[nil "\300\301!\207" [vhdl-template-directive "translate_on"] 2 (#$ . 328604) nil])
#@35 Insert directive 'translate_off'.
(defalias 'vhdl-template-directive-translate-off #[nil "\300\301!\207" [vhdl-template-directive "translate_off"] 2 (#$ . 328776) nil])
#@34 Insert directive 'synthesis_on'.
(defalias 'vhdl-template-directive-synthesis-on #[nil "\300\301!\207" [vhdl-template-directive "synthesis_on"] 2 (#$ . 328951) nil])
#@35 Insert directive 'synthesis_off'.
(defalias 'vhdl-template-directive-synthesis-off #[nil "\300\301!\207" [vhdl-template-directive "synthesis_off"] 2 (#$ . 329123) nil])
#@28 Insert a VHDL file header.
(defalias 'vhdl-template-header #[(&optional file-title) "\303\232?\205\304\212eb\210\305!\210\306 )\307\310 	\n#)\207" [vhdl-file-header pos file-title "" nil vhdl-insert-string-or-file point-marker vhdl-template-replace-header-keywords point-min-marker] 4 (#$ . 329298) nil])
#@28 Insert a VHDL file footer.
(defalias 'vhdl-template-footer #[nil "\302\232?\205$\303\212db\210\304 \305!\210h\306U\204\307c\210)\310	\311 \")\207" [vhdl-file-footer pos "" nil point-marker vhdl-insert-string-or-file 10 "\n" vhdl-template-replace-header-keywords point-max-marker] 3 (#$ . 329615) nil])
#@40 Replace keywords in header and footer.
(defalias 'vhdl-template-replace-header-keywords #[(beg end &optional file-title is-model) "\306	\"@\206	\307\310\306	\"8\206\307\311\312\313 \311\211\211@ABC\314D!\210\315\316!\203d\316 A\317A@AA\"\211A\203dA@\320\321
!>\203[
@B@\322
\320\311#\210AA\211A\204C\323\216\212Eb\210\324\325F\312#\203}\326\312\211#\210\202kEb\210\324\327F\312#\203\224\326\330 \312\211#\210\202\201Eb\210\324\331F\312#\203\253\326G\312\211#\210\202\230Eb\210\324\332F\312#\203\321\326\307\312\211#\210\333 c\210H\203\257\334H\335\261\210\202\257Eb\210\324\336F\312#\203\350\326\333 \312\211#\210\202\325Eb\210\324\337F\312#\203\377\326\340 \312\211#\210\202\354Eb\210\324\341F\312#\203
\326\f\312\211#\210\202
Eb\210\324\342F\312#\203,
\326I\312\211#\210\202
Eb\210\324\343F\312#\203C
\326J\312\211#\210\2020
Eb\210\324\344F\312#\203y
\326\345\346\347!\203\\
\350\202c
\346\351!\205c
\352\346\353!\205j
\354\346\355!\205q
\356R\312\211#\210\202G
Eb\210\324\357F\312#\203\217
\326\360\311\312#\210\202}
Eb\210\324\361F\312#\203\250
\326\307\312\211#\210\362 \210\202\223
Eb\210\324\363F\312#\203\301
\326\364\365\311\"\312\211#\210\202\254
Eb\210K\203\341
\324\366F\312#\203\335
\326K\312\211#\210\202\312
Eb\210\311L\367\370F\312#\203\371\372\373!\374P!L\326L\312\211#\210\202\344
)Eb\210M\204\324\375F\312#\203\326\307\312\211#\210`)\n\203#\nb\210M?\205`\f\2033\f\307\232\2037\376\377!\210\203A\307\232\203G\376\201N!\210J\307\232\203T\376\201O!\210I\307\232\205`\376\201P!.	\207" [vhdl-project-alist vhdl-project pos project-desc project-title overlay aget "" 9 nil t syntax-table set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) search-forward "<projectdesc>" replace-match "<filename>" buffer-name "<copyright>" "<author>" user-full-name "  <" ">" "<authorfull>" "<login>" user-login-name "<project>" "<company>" "<platform>" "<standard>" "VHDL" vhdl-standard-p 87 "'87" 93 "'93/02" ams ", VHDL-AMS" math ", Math Packages" "<RCS>" "$" "<date>" vhdl-template-insert-date "<year>" format-time-string "%Y" "<title string>" re-search-forward "<\\(\\(\\w\\|\\s_\\)*\\) string>" read-string match-string 1 ": " "<cursor>" message "You can specify a project title in user option `vhdl-project-alist'" overlay-intangible-list overlay-all-list current-syntax-table case-fold-search vhdl-mode-ext-syntax-table beg end vhdl-copyright-string user-mail-address vhdl-company-name vhdl-platform-spec file-title string is-model "You can specify a project description in user option `vhdl-project-alist'" "You can specify a platform in user option `vhdl-platform-spec'" "You can specify a company name in user option `vhdl-company-name'"] 7 (#$ . 329930)])
#@18 Indent comments.
(defalias 'vhdl-comment-indent #[nil "`\303y\210\304\305\306#\203i\307Z\202b\210\310\311x\210	iT]b\210\n*\207" [position comment-column col -1 re-search-forward "--" t 2 " 	" nil] 4 (#$ . 332951)])
#@153 Start a comment at the end of the line.
If on line with code, indent at least `comment-column'.
If starting after end-comment-column, start a new line.
(defalias 'vhdl-comment-insert #[nil "iV\203	\306 \210\307\310!\204	\204K\311\204K\311h\312U\203'\313\314!\210\202i\315 \210n\2039\nj\210\316c\210\202B\317c\210j\210\316c\210	?\205I\320c)\207\311\211h\312U\203\\\313\321!\210\202O\322 \211\323U\203w\316c\210\321u\210\324y\210\325\326!\210\327\202\\\f\204~\316c\210\330
!C\211*\207" [end-comment-column unread-command-events margin comment-column code next-input newline-and-indent looking-at "\\s-*$" nil 45 delete-char -1 delete-horizontal-space "--" "  " " " -2 read-char 13 1 message "Enter CR if commenting out a line of code." t vhdl-character-to-event] 2 (#$ . 333182) nil])
#@70 Add 2 comment lines at the current indent, making a display comment.
(defalias 'vhdl-comment-display #[(&optional line-exists) "\302 	\204\n\303 \210\304c\210j\210\304c\210j\210\303 \210\305\210\306c)\207" [margin line-exists current-indentation vhdl-comment-display-line "\n" 0 "-- "] 1 (#$ . 333997) nil])
#@30 Displays one line of dashes.
(defalias 'vhdl-comment-display-line #[nil "h\304U\203
\305\306!\210\202\307c\210i	Z\310\n\"*\207" [col end-comment-column len vhdl-comment-display-line-char 45 delete-char -2 "--" insert-char] 3 (#$ . 334316) nil])
#@46 Append empty inline comment to current line.
(defalias 'vhdl-comment-append-inline #[nil "\301\210\302 \210\303c\210j\210\304c\207" [comment-column nil delete-horizontal-space "  " "-- "] 1 (#$ . 334574) nil])
#@24 Insert inline comment.
(defalias 'vhdl-comment-insert-inline #[(&optional string always-insert) "\203\f	\204\n\204?\205F\205F`\306c\210
j\210\307c\210\203*c\210\2028\310\311\312\313#\2048\f`|\202Eh\314U\205E\315\316!\210\2028)\207" [string vhdl-self-insert-comments always-insert vhdl-prompt-for-comments position comment-column "  " "-- " vhdl-template-field "[comment]" nil t 32 delete-char -1] 4 (#$ . 334792)])
#@32 Insert comment for code block.
(defalias 'vhdl-comment-block #[nil "\205\216\306 \307\310 \311\211\211\312!\210\313\314!\203H\314 \315\f@\fA\"\211\203H\f@\316\317\n!>\203A\nB\320\n\316\311#\210\fA\211\204,\321\216\322\323\311\307#\203\211\322\324\311\307#\203\211\311\325 \210i\326\210o\203s\327c\210\330y\210\202v\327c\210j\210\331c\210\332\333\311\307#\204\210\334 \210).	b)\207" [vhdl-prompt-for-comments final-pos overlay overlay-intangible-list overlay-all-list current-syntax-table point-marker t syntax-table nil set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) re-search-backward "^\\s-*begin\\>" "\\<\\(architecture\\|block\\|function\\|procedure\\|process\\|procedural\\)\\>" back-to-indentation 0 "\n" -1 "-- purpose: " vhdl-template-field "[description]" vhdl-line-kill-entire case-fold-search vhdl-mode-ext-syntax-table margin] 6 (#$ . 335232)])
#@63 Comment out region if not commented out, uncomment otherwise.
(defalias 'vhdl-comment-uncomment-region #[(beg end &optional arg) "\212Sb\210\303\210\304 	b\210\305 \210`\306\307\nP!\203#\310	\311#\202'\310	\")\207" [end beg comment-start nil point-marker beginning-of-line looking-at "\\s-*" comment-region (4)] 4 (#$ . 336372) "r\nP"])
#@61 Comment out line if not commented out, uncomment otherwise.
(defalias 'vhdl-comment-uncomment-line #[(&optional arg) "\212\302 \210`	\206\303y\210\304`\"*\207" [position arg beginning-of-line 1 vhdl-comment-uncomment-region] 3 (#$ . 336723) "p"])
#@26 Kill comments in region.
(defalias 'vhdl-comment-kill-region #[(beg end) "\212b\210\302 	b\210\303 \210`W\205)\304\305!\203\"\306\224\306\225|\210\202
\303\307!\210\202
)\207" [end beg point-marker beginning-of-line looking-at "^\\(\\s-*--.*\n\\)" 1 2] 2 (#$ . 336980) "r"])
#@33 Kill inline comments in region.
(defalias 'vhdl-comment-kill-inline-region #[(beg end) "\212b\210\302 	b\210\303 \210`W\205&\304\305!\203\306\224\306\225|\210\303\307!\210\202
)\207" [end beg point-marker beginning-of-line looking-at "^.*[^ 	\n
\f-]+\\(\\s-*--.*\\)$" 1 2] 2 (#$ . 337268) "r"])
#@91 Insert a begin ... end pair with optional name after the end.
Point is left between them.
(defalias 'vhdl-template-begin-end #[(construct name margin &optional empty-lines) "\306	\204\f\n\307=\203\310c\210j\210\311\312!\210\f\204
\203:\203:\313c\210\f\2031\314c\210\311\f!\210
\203:\314
\261\210\310c\210	\204G\n\307=\203J\310c\210\\j\210`\310c\210	\204_\n\307=\203b\310c\210j\210\311\315!\210\f\203t\314c\210\311\f!\210
\203~\314
P\202\316\317\261\210b)\207" [position empty-lines vhdl-insert-empty-lines margin construct name nil all "\n" vhdl-insert-keyword "BEGIN" "  --" " " "END" "" ";" vhdl-self-insert-comments vhdl-basic-offset] 2 (#$ . 337576)])
#@55 Read from user a procedure or function argument list.
(defalias 'vhdl-template-argument-list #[(&optional is-function) "\306c\210i``\307\211\211\204 \310 \\\311c\210
j\210\312\313?\205)\314\315Q\316\317#\312\320\307\317#\203\317\321c\210\204Y	\203S	\226\322\232\203S\323\324!\210\202Y\312\325\316\317#\210\312\326!\210`\327c\210\330 \210`\311c\210
j\210\312\313?\205v\314\315Q\316\317#\202/`|\210\203\212b\210\n\203\227\331\332!\210\333c\202\232\331\334!.\207" [semicolon-pos interface not-empty end-pos start margin " (" nil current-indentation "\n" vhdl-template-field "[CONSTANT | SIGNAL" " | VARIABLE" "]" " " t "[names]" " : " "CONSTANT" vhdl-insert-keyword "IN " "[IN | OUT | INOUT]" "type" ";" vhdl-comment-insert-inline delete-char 1 ")" -2 vhdl-argument-list-indent vhdl-basic-offset is-function] 6 (#$ . 338267)])
#@46 Read from user a generic spec argument list.
(defalias 'vhdl-template-generic-list #[(optional &optional no-value) "\306`\307\310!\210i\n\204!`\311 \210i\f\\b\210\312c\210	j\210)\313
\205'\314\315 \205.\316
\2053\317R\306
#\211!\204]
\203T\320 \210\321\210\n?\205\315\320 \210\321\202\315\322`\"\210\306\202\315\323c\210\306\211\"#!\203\261\313\324!\210 \203}`#\325c\210\202\222\326c\210\313\327\306\330#\204\214\331\332!\210`#\325c\210\333 \210`\"\312c\210	j\210\313\334 \205\246\316\317Q\323\330#\211!\204k\"`|\210#b\210\335c\210\306\210$\203\313\336`\337#\210*\330+\207" [start margin vhdl-argument-list-indent position vhdl-basic-offset optional nil vhdl-insert-keyword "GENERIC (" back-to-indentation "\n" vhdl-template-field "[" "name" "s" "]" vhdl-line-kill-entire 0 vhdl-template-undo " : " "type" ";" " := " "[value]" t delete-char -4 vhdl-comment-insert-inline "[name" ")" vhdl-align-region-groups 1 no-value vhdl-generics end-pos semicolon-pos vhdl-auto-align] 6 (#$ . 339136)])
#@43 Read from user a port spec argument list.
(defalias 'vhdl-template-port-list #[(optional) "`\306\211\211\307\310!\210i\f\204&`\311 \210i%\\
b\210\312c\210\nj\210)\313\314!\2032\315\316\317\320#\315&\2059\321\322&\205@\323Q\306&#\211\204k&\203b\324 \210\325\210\f?\205\360\324 \210\325\202\360\326`\"\210\306\202\360\327c\210\306\211'(	\203\323\203\203\226\330\232\203\213\315\331\317\"\210\202\230\226\332\232\203\230\315\333\317\320#\210\315\203\250\226\334\232\203\250\335\202\251\336!\210`(\337c\210\340 \210`'\312c\210\nj\210\313\314!\203\311\315\316\317\320#\315\341\327\320#\211\204x'`|\210(b\210\342c\210\306\210)\203\356\343'\344#\210*\320,\207" [object vhdl-ports margin start vhdl-argument-list-indent position nil vhdl-insert-keyword "PORT (" back-to-indentation "\n" vhdl-standard-p ams vhdl-template-field "[SIGNAL | TERMINAL | QUANTITY]" " " t "[" "names" "]" vhdl-line-kill-entire 0 vhdl-template-undo " : " "SIGNAL" "IN | OUT | INOUT" "QUANTITY" "[IN | OUT]" "TERMINAL" "nature" "type" ";" vhdl-comment-insert-inline "[names]" ")" vhdl-align-region-groups 1 vhdl-basic-offset optional end-pos semicolon-pos vhdl-auto-align] 5 (#$ . 340173)])
#@36 Insert body for generate template.
(defalias 'vhdl-template-generate-body #[(margin label) "\303\304!\210\305c\210j\210\303\306!\210	\307\261\210\310\210\n\\j\207" [margin label vhdl-basic-offset vhdl-insert-keyword " GENERATE" "\n\n" "END GENERATE " ";" 0] 2 (#$ . 341391)])
#@36 Insert date in appropriate format.
(defalias 'vhdl-template-insert-date #[nil "\301=\203
\302\303\304\"\202+\305=\203\302\306\304\"\202+\307=\203'\302\310\304\"\202+\302\304\"c\207" [vhdl-date-format american format-time-string "%m/%d/%Y" nil european "%d.%m.%Y" scientific "%Y/%m/%d"] 3 (#$ . 341677) nil])
#@118 Expand abbreviations and self-insert space(s), do indent-new-comment-line
if in comment and past end-comment-column.
(defalias 'vhdl-electric-space #[(count) "\306 \203-\307!\210i\310	\\Y\203\"\311u\210\312\313x\210\314 \210\312\313w\210\315u\207i	Y\203+\314 \207\313\207h\316Y\2039h\317X\204Eh\320Y\203`h\321X\203`\322\323 p\324\216\325
!\210\326 \204[\327\311!\210,\307!\207\307!\207" [count end-comment-column case-fold-search #1=#:buffer #2=#:table vhdl-mode-ext-syntax-table vhdl-in-comment-p self-insert-command 2 -1 "^ 	\n
\f" nil indent-new-comment-line 1 97 122 65 90 t syntax-table ((byte-code "rq\210\302	!\210)\302\207" [#1# #2# set-syntax-table] 2)) set-syntax-table expand-abbrev vhdl-fix-case-word] 3 (#$ . 342003) "p"])
#@368 Prompt for string and insert it in buffer with optional FOLLOW-STRING.
If OPTIONAL is nil, the prompt is left if an empty string is inserted.  If
an empty string is inserted, return nil and call `vhdl-template-undo' for
the region between BEGIN and END.  IS-STRING indicates whether a string
with double-quotes is to be inserted.  DEFAULT specifies a default string.
(defalias 'vhdl-template-field #[(prompt &optional follow-string optional begin end is-string default) "`\306\307\n\310\261\210\306\311\312\217\211\313\232\203\203	`|\210\313\232\2038\2038\f\2038
\2038\314\f
\"\210\315\316!\210\313\232\204pc\210\317	`$\210\317	`$\210\317	`\320P$\210\317	`$\210\317	`$\210\313\232\203z\204\202\206\200\313c\210\313\232?\205\212*\207" [string position prompt optional begin end nil "<" ">" (byte-code "\304\305P	\203\f\306\202
\n#\207" [prompt is-string default vhdl-minibuffer-local-map read-from-minibuffer ": " ("\"\"" . 2)] 4) ((quit (byte-code "\203	\203\n\203\303 \210\304\207\305 \207" [optional begin end beep #1="" keyboard-quit] 1))) #1# vhdl-template-undo message "Template aborted" vhdl-fix-case-region-1 "'" vhdl-upper-case-keywords vhdl-keywords-regexp vhdl-upper-case-types vhdl-types-regexp vhdl-upper-case-attributes vhdl-attributes-regexp vhdl-upper-case-enum-values vhdl-enum-values-regexp vhdl-upper-case-constants vhdl-constants-regexp follow-string] 7 (#$ . 342761)])
#@33 Query a decision from the user.
(defalias 'vhdl-decision-query #[(string prompt &optional optional) "`	\203\f\305	\306P!\210\307\310\n\206\311\"\210\312 `|\210\f\2033\313=\2033\306c\210\314 \210\315\316\317\"\2024*\207" [start string prompt char optional vhdl-insert-keyword " " message "%s" "" read-char 13 unexpand-abbrev throw abort "ERROR:  Template aborted"] 3 (#$ . 344215)])
#@33 Insert KEYWORD and adjust case.
(defalias 'vhdl-insert-keyword #[(keyword) "\203		\226\202	\227c\207" [vhdl-upper-case-keywords keyword] 1 (#$ . 344614)])
#@25 Adjust case of KEYWORD.
(defalias 'vhdl-case-keyword #[(keyword) "\203	\226\207	\227\207" [vhdl-upper-case-keywords keyword] 1 (#$ . 344779)])
#@37 Adjust case of following NUM words.
(defalias 'vhdl-case-word #[(num) "\203\302	!\207\303	!\207" [vhdl-upper-case-keywords num upcase-word downcase-word] 2 (#$ . 344931)])
#@136 If preceding character is part of a word or a paren then hippie-expand,
else insert tab (used for word completion in VHDL minibuffer).
(defalias 'vhdl-minibuffer-tab #[(&optional prefix-arg) "hz\305U\203?\306\307\301!\203	\206\310\311\f!+\207h\312U\204)h\313U\2033?\306\314\f!*\207\315 \207" [vhdl-word-completion-case-sensitive hippie-expand-only-buffers case-replace case-fold-search prefix-arg 119 nil boundp (vhdl-mode) vhdl-expand-abbrev 40 41 vhdl-expand-paren insert-tab] 4 (#$ . 345113) "P"])
#@55 Search for left out template prompts and query again.
(defalias 'vhdl-template-search-prompt #[nil "\306\307 \310\211\211\311
!\210\312\313!\203?\313 \314\n@\nA\"\211\203?\n@\315\316!>\2038	B\317\315\310#\210\nA\211\204#\320\216\321\322\323Q\310\306#\204Y\324\322\323Q\310\306#\205g\325\326!\327\330!\210\331!).\207" [overlay overlay-intangible-list overlay-all-list current-syntax-table case-fold-search vhdl-mode-ext-syntax-table t syntax-table nil set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) re-search-forward "<\\(" "\\)>" re-search-backward match-string 1 replace-match "" vhdl-template-field vhdl-template-prompt-syntax string] 6 (#$ . 345635) nil])
#@71 Undo aborted template by deleting region and unexpanding the keyword.
(defalias 'vhdl-template-undo #[(begin end) "\203	b\210\303c\210\n	|\210\304 \207\n	|\207" [vhdl-template-invoked-by-hook end begin " " unexpand-abbrev] 2 (#$ . 346571)])
#@68 Insert STRING or file contents if STRING is an existing file name.
(defalias 'vhdl-insert-string-or-file #[(string) "\303\232?\205(\304\305\"\210\306\307\310\"!\311	!\203%\312	!\211A@)u\202'c)\207" [string file-name x "" string-match "^\\([^\n]+\\)" vhdl-resolve-env-variable match-string 1 file-exists-p insert-file-contents] 5 (#$ . 346821)])
#@54 Move cursor to the beginning of the enclosing block.
(defalias 'vhdl-beginning-of-block #[nil "\306\307\310 \306\211\211\311%!\210\312\313!\203B\313 \314@A\"\211\203B@\315\316	!>\203;	\nB\317	\315\306#\210A\211\204&\320\216\212\321 \210\322\323\306\307#\211\203\232\324\325!\203\200\326 &\327\216\212\325\225b\210\330v\210\331 \210\332\333!\203r\334 \210\335\336\306\307#\210)\324\330!*\204H\324\337!\203\232\326 &\340\216\212\341 \210\321 \210\332\342!+\203H\324\343!\203\246\344 \210\202H.\205\256b)\207" [pos overlay overlay-intangible-list overlay-all-list current-syntax-table case-fold-search nil t syntax-table set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) beginning-of-line re-search-backward "^\\s-*\\(\\(end\\)\\|\\(\\(impure\\|pure\\)[ 	\n
\f]+\\)?\\(function\\|procedure\\)\\|\\(for\\)\\|\\(architecture\\|component\\|configuration\\|entity\\|package\\(\\s-+body\\)?\\|type[ 	\n
\f]+\\w+[ 	\n
\f]+is[ 	\n
\f]+\\(record\\|protected\\(\\s-+body\\)?\\)\\|units\\)\\|\\(\\w+[ 	\n
\f]*:[ 	\n
\f]*\\)?\\(postponed[ 	\n
\f]+\\)?\\(block\\|case\\|for\\|if\\|procedural\\|process\\|while\\|loop\\)\\)\\>" match-string 5 match-data ((byte-code "\301\302\"\207" [save-match-data-internal set-match-data evaporate] 3)) 1 vhdl-forward-syntactic-ws looking-at "(" forward-sexp re-search-forward "\\<is\\>\\|\\(;\\)" 6 ((byte-code "\301\302\"\207" [save-match-data-internal set-match-data evaporate] 3)) vhdl-end-of-block "^\\s-*end\\s-+\\(for\\|generate\\|loop\\)\\>" 2 vhdl-beginning-of-block vhdl-mode-ext-syntax-table save-match-data-internal] 6 (#$ . 347181)])
#@48 Move cursor to the end of the enclosing block.
(defalias 'vhdl-end-of-block #[nil "\306\307\310 \306\211\211\311 !\210\312\313!\203B\313 \314@A\"\211\203B@\315\316	!>\203;	\nB\317	\315\306#\210A\211\204&\320\216\212\306\210\321\322\306\307#\211\203\207\323\324!\203m\325 !\326\216\212\321\327\306\307#\210)\323\330!*\204H\323\331!\203\207\325 !\332\216\212\333 \210\334 \210\335\336!+\203H\323\337!\204\223\333 \210\202H.\205\233b)\207" [pos overlay overlay-intangible-list overlay-all-list current-syntax-table case-fold-search nil t syntax-table set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) re-search-forward "^\\s-*\\(\\(end\\)\\|\\(\\(impure\\|pure\\)[ 	\n
\f]+\\)?\\(function\\|procedure\\)\\|\\(for\\)\\|\\(architecture\\|component\\|configuration\\|entity\\|package\\(\\s-+body\\)?\\|type[ 	\n
\f]+\\w+[ 	\n
\f]+is[ 	\n
\f]+\\(record\\|protected\\(\\s-+body\\)?\\)\\|units\\)\\|\\(\\w+[ 	\n
\f]*:[ 	\n
\f]*\\)?\\(postponed[ 	\n
\f]+\\)?\\(block\\|case\\|for\\|if\\|procedural\\|process\\|while\\|loop\\)\\)\\>" match-string 5 match-data ((byte-code "\301\302\"\207" [save-match-data-internal set-match-data evaporate] 3)) "\\<is\\>\\|\\(;\\)" 1 6 ((byte-code "\301\302\"\207" [save-match-data-internal set-match-data evaporate] 3)) vhdl-end-of-block beginning-of-line looking-at "^\\s-*end\\s-+\\(for\\|generate\\|loop\\)\\>" 2 vhdl-mode-ext-syntax-table save-match-data-internal] 6 (#$ . 349031)])
#@53 Check if point is within sequential statement part.
(defalias 'vhdl-sequential-statement-p #[nil "`\212\306\307 \310\211\211\311!\210\312\313!\203C\313 \314@A\"\211\203C@\315\316	!>\203<	\nB\317	\315\310#\210A\211\204'\320\216\321\322\310\306#\205\\\323 \210`W\205\\\324 \210\325\326!.\207" [start overlay overlay-intangible-list overlay-all-list current-syntax-table case-fold-search t syntax-table nil set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) re-search-backward "^\\s-*begin\\>" vhdl-end-of-block vhdl-beginning-of-block looking-at "^\\s-*\\(\\(\\w+[ 	\n
\f]+\\)?\\(function\\|procedure\\)\\|\\(\\w+[ 	\n
\f]*:[ 	\n
\f]*\\)?\\(\\w+[ 	\n
\f]+\\)?\\(procedural\\|process\\)\\)\\>" vhdl-mode-ext-syntax-table] 6 (#$ . 350725)])
#@35 Check if within an argument list.
(defalias 'vhdl-in-argument-list-p #[nil "\212\306\307 \310\211\211\311
!\210\312\313!\203@\313 \314\n@\nA\"\211\203@\n@\315\316!>\2039	B\317\315\310#\210\nA\211\204$\320\216\321\322\323\324\325 \211@@)\"\"\206Y\326 \210\327\330!.\207" [overlay overlay-intangible-list overlay-all-list current-syntax-table case-fold-search vhdl-mode-ext-syntax-table t syntax-table nil set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) string-match "arglist" format "%s" vhdl-get-syntactic-context beginning-of-line looking-at "^\\s-*\\(generic\\|port\\|\\(\\(impure\\|pure\\)\\s-+\\|\\)function\\|procedure\\)\\>\\s-*\\(\\w+\\s-*\\)?(" x] 6 (#$ . 351732)])
#@114 Do function, if syntax says abbrev is a keyword, invoked by hooked abbrev,
but not if inside a comment or quote.
(defalias 'vhdl-hooked-abbrev #[(func) "\306 \204\212\307v\210\310\311!\205\310\312!?)\203(\313c\210\314 \210\307v\210\315\316!\210\317\316!\207\204=\313c\210\314 \210\307v\210\315\316!\210\317\316!\207	\307\320\321\322\215\211;\203Q\323\324
\"\210)\f\325U\203[`\326\327!\203h\327\317\307\"\202o\330\331!C\211+\207" [vhdl-electric-mode last-command-event vhdl-template-invoked-by-hook abbrev-mode invoke-char caught vhdl-in-literal -1 looking-at "\\<end\\>" "\\<end;" " " unexpand-abbrev vhdl-case-word 1 delete-char t abort (funcall func) message "%s" 45 fboundp enqueue-eval-event vhdl-character-to-event 127 abbrev-start-location unread-command-events] 4 (#$ . 352676)])
(defalias 'vhdl-template-alias-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-alias] 2])
(defalias 'vhdl-template-architecture-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-architecture] 2])
(defalias 'vhdl-template-assert-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-assert] 2])
(defalias 'vhdl-template-attribute-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-attribute] 2])
(defalias 'vhdl-template-block-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-block] 2])
(defalias 'vhdl-template-break-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-break] 2])
(defalias 'vhdl-template-case-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-case] 2])
(defalias 'vhdl-template-component-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-component] 2])
(defalias 'vhdl-template-instance-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-instance] 2])
(defalias 'vhdl-template-conditional-signal-asst-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-conditional-signal-asst] 2])
(defalias 'vhdl-template-configuration-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-configuration] 2])
(defalias 'vhdl-template-constant-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-constant] 2])
(defalias 'vhdl-template-disconnect-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-disconnect] 2])
(defalias 'vhdl-template-display-comment-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-comment-display] 2])
(defalias 'vhdl-template-else-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-else] 2])
(defalias 'vhdl-template-elsif-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-elsif] 2])
(defalias 'vhdl-template-entity-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-entity] 2])
(defalias 'vhdl-template-exit-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-exit] 2])
(defalias 'vhdl-template-file-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-file] 2])
(defalias 'vhdl-template-for-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-for] 2])
(defalias 'vhdl-template-function-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-function] 2])
(defalias 'vhdl-template-generic-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-generic] 2])
(defalias 'vhdl-template-group-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-group] 2])
(defalias 'vhdl-template-library-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-library] 2])
(defalias 'vhdl-template-limit-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-limit] 2])
(defalias 'vhdl-template-if-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-if] 2])
(defalias 'vhdl-template-bare-loop-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-bare-loop] 2])
(defalias 'vhdl-template-map-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-map] 2])
(defalias 'vhdl-template-nature-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-nature] 2])
(defalias 'vhdl-template-next-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-next] 2])
(defalias 'vhdl-template-others-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-others] 2])
(defalias 'vhdl-template-package-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-package] 2])
(defalias 'vhdl-template-port-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-port] 2])
(defalias 'vhdl-template-procedural-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-procedural] 2])
(defalias 'vhdl-template-procedure-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-procedure] 2])
(defalias 'vhdl-template-process-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-process] 2])
(defalias 'vhdl-template-quantity-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-quantity] 2])
(defalias 'vhdl-template-report-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-report] 2])
(defalias 'vhdl-template-return-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-return] 2])
(defalias 'vhdl-template-selected-signal-asst-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-selected-signal-asst] 2])
(defalias 'vhdl-template-signal-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-signal] 2])
(defalias 'vhdl-template-subnature-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-subnature] 2])
(defalias 'vhdl-template-subtype-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-subtype] 2])
(defalias 'vhdl-template-terminal-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-terminal] 2])
(defalias 'vhdl-template-type-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-type] 2])
(defalias 'vhdl-template-use-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-use] 2])
(defalias 'vhdl-template-variable-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-variable] 2])
(defalias 'vhdl-template-wait-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-wait] 2])
(defalias 'vhdl-template-when-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-when] 2])
(defalias 'vhdl-template-while-loop-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-while-loop] 2])
(defalias 'vhdl-template-with-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-with] 2])
(defalias 'vhdl-template-and-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-and] 2])
(defalias 'vhdl-template-or-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-or] 2])
(defalias 'vhdl-template-nand-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-nand] 2])
(defalias 'vhdl-template-nor-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-nor] 2])
(defalias 'vhdl-template-xor-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-xor] 2])
(defalias 'vhdl-template-xnor-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-xnor] 2])
(defalias 'vhdl-template-not-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-not] 2])
(defalias 'vhdl-template-default-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-default] 2])
(defalias 'vhdl-template-default-indent-hook #[nil "\300\301!\207" [vhdl-hooked-abbrev vhdl-template-default-indent] 2])
#@51 Insert the built-in construct template with NAME.
(defalias 'vhdl-template-insert-construct #[(name) "\303\304	\"\211A@)!\207" [name vhdl-template-construct-alist x vhdl-template-insert-fun assoc] 5 (#$ . 359873) (list (let ((completion-ignore-case t)) (completing-read "Construct name: " vhdl-template-construct-alist nil t)))])
#@49 Insert the built-in package template with NAME.
(defalias 'vhdl-template-insert-package #[(name) "\303\304	\"\211A@)!\207" [name vhdl-template-package-alist x vhdl-template-insert-fun assoc] 5 (#$ . 360211) (list (let ((completion-ignore-case t)) (completing-read "Package name: " vhdl-template-package-alist nil t)))])
#@51 Insert the built-in directive template with NAME.
(defalias 'vhdl-template-insert-directive #[(name) "\303\304	\"\211A@)!\207" [name vhdl-template-directive-alist x vhdl-template-insert-fun assoc] 5 (#$ . 360539) (list (let ((completion-ignore-case t)) (completing-read "Directive name: " vhdl-template-directive-alist nil t)))])
#@41 Call FUN to insert a built-in template.
(defalias 'vhdl-template-insert-fun #[(fun) "\301\302\215\211;\205
\303\304\")\207" [caught abort (byte-code "\205 \207" [fun] 1) message "%s"] 4 (#$ . 360877)])
#@45 Insert the user model with name MODEL-NAME.
(defalias 'vhdl-model-insert #[(model-name) "\306 \210\307 \310 \311\211\211\211\211*\312\313 \311\211\211+,-./\3140!\210\315\316!\203f\316 -\317-@-A\"\211-\203f-@+\320\321+!>\203]+,B,\322+\320\311#\210-A\211-\204A\323\216\32412\"\211\205<
\325 \210\326 \210*b\210\327\fA@!\210\307 *b\210\325 \210`W\203\245\330\331!\204\236\332\333
\"\210\325\334!\210\202\215*b\2103\335\232\204\300\336\337\312#\203\300\3403!\210\202\260*b\2104\335\232\204\333\336\341\312#\203\333\3404!\210\202\313\342*\311\312$\210*b\210\336\3435\344Q\312#\203(
\345\346!\347\232\204\347\346\224\345\346!\340\335!\210\350\n\311\312#\336\343\n\344Q\312#\203\"
\340	\206
\335!\210\202\f
b\210\202\347*b\210\336\351\312#\203:
\340\335!\202<
b.
\207" [end string prompt position model margin indent-according-to-mode point-marker current-indentation nil t syntax-table set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) assoc beginning-of-line delete-horizontal-space vhdl-insert-string-or-file looking-at "^$" insert-char 32 2 "" re-search-forward "<clock>" replace-match "<reset>" vhdl-template-replace-header-keywords "<\\(" "\\)>" match-string 1 "cursor" vhdl-template-field "<cursor>" start overlay overlay-intangible-list overlay-all-list current-syntax-table case-fold-search vhdl-mode-ext-syntax-table model-name vhdl-model-alist vhdl-clock-name vhdl-reset-name vhdl-template-prompt-syntax] 8 (#$ . 361092) (let ((completion-ignore-case t)) (list (completing-read "Model name: " vhdl-model-alist)))])
#@49 Define help and hook functions for user models.
(defalias 'vhdl-model-defun #[nil "\304\211\211\205G@@\305\306\307\310\n\"\304\311\n\312Q\313\314\nD\257!\210\315@8\211\316\232\204?\305\306\307\310\n\317#\304\320\321\307\310\n\"DDF!\210A\211\204\n\304+\207" [vhdl-model-alist model-keyword model-name model-alist nil eval defun vhdl-function-name "vhdl-model" "Insert model for \"" "\"." (interactive) vhdl-model-insert 3 "" "hook" vhdl-hooked-abbrev quote] 10 (#$ . 362927)])
(vhdl-model-defun)
#@40 Variable to hold last port map parsed.
(defvar vhdl-port-list nil (#$ . 363442))
#@67 Check that the text following point matches the regexp in STRING.
(defalias 'vhdl-parse-string #[(string &optional optional) "\302!\203\303\225b\210\304 \203\305\210`\207	\204\"\306\307\310\311\312 #\"\210\305\207" [string optional looking-at 0 vhdl-in-literal nil throw parse format "ERROR:  Syntax error near line %s, expecting \"%s\"" vhdl-current-line] 6 (#$ . 363529)])
#@63 Replace STRING from car of REGEXP-CONS to cdr of REGEXP-CONS.
(defalias 'vhdl-replace-string #[(regexp-cons string &optional adjust-case) "\306\307 p\310\216\311!\210\312\f@
\"\2031
\203'\313\fA\306\314
$!\2022\313\fA\306\314
$\2022
,\207" [case-fold-search #1=#:buffer #2=#:table vhdl-mode-ext-syntax-table regexp-cons string t syntax-table ((byte-code "rq\210\302	!\210)\302\207" [#1# #2# set-syntax-table] 2)) set-syntax-table string-match replace-match nil adjust-case vhdl-file-name-case] 6 (#$ . 363918)])
#@56 Parse comment and empty lines between groups of lines.
(defalias 'vhdl-parse-group-comment #[nil "`\302\303d!\210\304	`\"\305 \210\306\307\"\203&\310\311\224O\311\225\302OP\202\312\232\204<\310\311O\313\232\203<\311\302O\202=*\207" [string start nil vhdl-forward-comment buffer-substring-no-properties vhdl-forward-syntactic-ws string-match "^\\(\\s-+\\)" 0 1 "" "\n"] 4 (#$ . 364448)])
#@80 Paste comment and empty lines from STRING between groups of lines
with INDENT.
(defalias 'vhdl-paste-group-comment #[(string indent) "\303 	\304V\203#\305\306\n\"\203#\n\304\307\224O\310	\311\"\n\307\224\312OQ\202	\313 \210\nc\210b)\207" [pos indent string point-marker 0 string-match "^\\(--\\)" 1 make-string 32 nil beginning-of-line] 5 (#$ . 364858)])
#@46 Indicates whether a port has been flattened.
(defvar vhdl-port-flattened nil (#$ . 365225))
#@178 Flatten port list so that only one generic/port exists per line.
This operation is performed on an internally stored port and is only
reflected in a subsequent paste operation.
(defalias 'vhdl-port-flatten #[(&optional as-alist) "\204\306\307!\207\310\311!\210@CA\312\211\211\211\211A\203n@\312
\203^
@\211@\211\203W\203C	@\202F	@CAB\313\f\nC\"	A\211\2049
A\211\204/A\313\fC\"\202\313C\"\314\310\315!.\207" [vhdl-port-list names new-port old-port new-port-list old-port-list error "ERROR:  No port has been read" message "Flattening port for next paste..." nil append t "Flattening port for next paste...done" old-vhdl-port-list new-vhdl-port-list as-alist vhdl-port-flattened] 8 (#$ . 365324) nil])
#@49 Indicates whether port directions are reversed.
(defvar vhdl-port-reversed-direction nil (#$ . 366084))
#@170 Reverse direction for all ports (useful in testbenches).
This operation is performed on an internally stored port and is only
reflected in a subsequent paste operation.
(defalias 'vhdl-port-reverse-direction #[nil "\204\306\307!\207\310\311!\210\3128\313\211\211\203V@\211AA)\211@\n	\314\232\203.\315\202M	\316\232\2038\317\202M	\315\232\203B\314\202M	\317\232\203L\316\202M	\240\210A\211\204
?\310\320!+\207" [vhdl-port-list port-dir port-dir-car port-list x vhdl-port-reversed-direction error "ERROR:  No port has been read" message "Reversing port directions for next paste..." 2 nil "in" "out" "IN" "OUT" "Reversing port directions for next paste...done"] 4 (#$ . 366195) nil])
#@75 Get generic and port information from an entity or component declaration.
(defalias 'vhdl-port-copy #[nil "\212\306\211\211\211\211\211\211\211\211\211\211\211\211\211\307\310 \306\211\211 \311!!\210\312\313!\203w\313 \314@A\"\211\203w@\315\316!>\203nB\317\315\306#\210A\211\204R\320\216\321\322\215.\203\214\323!\202\236F\"\306\211#\211$.\207" [group-comment comment init type direct names nil t syntax-table set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) parse (byte-code "\306\210\307\310\306\311#\203\312\313!\226\314\232\203\315\316\317\"\210\320\313!\227\313v\210\321\322!\210\320\313!\323\324	#\210\325 \210\321\326\311\"\203V
\327 \321\330\311\"\204V
\321\331!\210\320\313!C\321\332\311\"\203`\333\f\320\313!C\"\202N\321\334!\210\320\313!\335 \203y
\321\336!\205w\320\337!P\3066\340\341!\203\231
\342`\343 \210`\"\321\344\311\"\205\224\320\313!Q\202|
\203\261\345\346
\"\203\261
\347\224\306O6
\337\313\224O\345\350
\"\210
\337\313\225O\3067\321\351\311\"\203\356\321\352!\210\320\313!7\340\341!\203\3567\342`\343 \210`\"\321\352\311\"\205\350\320\313!Q7\202\3177\203
\345\3467\"\203
7\347\224\306O67\337\313\224O7\325 \210\353\306w\2106\204#
\321\354\311\"\205!
\320\313!6\325 \210\321\355\311\"\321\356!\2106\204@
\321\354\311\"\205>
\320\313!6\3338\f
76\n\257C\"8\327 \202A\321\357\311\"\2031\327 \321\330\311\"\2041\321\360\311\"\205s
\320\313!9\321\331!\210\320\313!C\321\332\311\"\203\220
\333\f\320\313!C\"\202~
\321\361!\210\321\362\311\"\205\236
\320\313!:\321\363!\210\320\313!\335 \203\271

\321\336!\205\267
\320\337!P\3066\340\341!\203\331

\342`\343 \210`\"\321\352\311\"\205\324
\320\313!Q\202\274

\203\361
\345\346
\"\203\361

\347\224\306O6
\337\313\224O\345\350
\"\210
\337\313\225O\325 \210\321\355\311\"\321\356!\2106\204\321\354\311\"\205\320\313!6\333;\f9:
6\n\257C\";\327 \202e
\364 <\323\365	#\210\306\207" [decl-type name group-comment end-of-list names type nil re-search-backward "^\\s-*\\(component\\|entity\\|end\\)\\>" t match-string 1 "END" throw parse "ERROR:  Not within an entity or component declaration" match-string-no-properties vhdl-parse-string "\\s-+\\(\\w+\\)\\(\\s-+is\\>\\)?" message "Reading port of %s \"%s\"..." vhdl-forward-syntactic-ws "generic[ 	\n
\f]*(" vhdl-parse-group-comment ")[ 	\n
\f]*;[ 	\n
\f]*" "\\(\\\\[^\\]+\\\\\\|\\w+\\)[ 	\n
\f]*" ",[ 	\n
\f]*\\(\\\\[^\\]+\\\\\\|\\w+\\)[ 	\n
\f]*" append ":[ 	\n
\f]*\\([^():;\n]+\\)" vhdl-in-comment-p ".*" 0 looking-at "(" buffer-substring-no-properties forward-sexp "\\([^():;\n]*\\)" string-match "\\(\\s-*--\\s-*\\)\\(.*\\)" 2 "\\(\\(\\s-*\\S-+\\)+\\)\\s-*" ":=[ 	\n
\f]*" "\\([^();\n]*\\)" " 	" "--\\s-*\\([^\n]*\\)" ")" "\\s-*;\\s-*" "port[ 	\n
\f]*(" "\\<\\(signal\\|quantity\\|terminal\\)\\>[ 	\n
\f]*" ":[ 	\n
\f]*" "\\<\\(in\\|out\\|inout\\|buffer\\|linkage\\)\\>[ 	\n
\f]+" "\\([^();\n]+\\)" vhdl-scan-context-clause "Reading port of %s \"%s\"...done" comment init generic-list object direct port-list context-clause] 8) error object context-clause port-list generic-list name decl-type end-of-list parse-error overlay overlay-intangible-list overlay-all-list current-syntax-table case-fold-search vhdl-mode-ext-syntax-table vhdl-port-list vhdl-port-reversed-direction vhdl-port-flattened] 15 (#$ . 366908) nil])
#@25 Paste a context clause.
(defalias 'vhdl-port-paste-context-clause #[(&optional exclude-pack-name) "\305 \3068\307\n\205A\n@\f\203	A\227\f\227\232\2049\212\310\311	@\312	A\313\260\307\314#)\2049\315	@	A\"\210\316c\210\nA\211\204
\307+\207" [vhdl-port-list clause clause-list margin exclude-pack-name current-indentation 3 nil re-search-backward "^\\s-*use\\s-+" "." "\\>" t vhdl-template-standard-package "\n"] 7 (#$ . 370562)])
#@25 Paste a generic clause.
(defalias 'vhdl-port-paste-generic #[(&optional no-init) "\306 A@\307\211\211\211
\205\251`\310\311!\210\204)\312c\210\\j\210i
\203\236
@\313>\203@\314\315	8\f\"\210	@\n\203X\n@c\210\nA\211\203C\316c\210\202C\317	A@\261\210\204q\320	8\203q\321\320	8\261\210
A\204y\322c\210\323c\210\203\216\324	8\203\216\325\324	8\326\"\210
A\211\203+\312c\210\fj\210\202+\205\251\327`\330\326$.\207" [vhdl-port-list generic names start list-margin generic-list current-indentation nil vhdl-insert-keyword "GENERIC (" "\n" (decl always) vhdl-paste-group-comment 4 ", " " : " 2 " := " ")" ";" 3 vhdl-comment-insert-inline t vhdl-align-region-groups 1 margin vhdl-argument-list-indent vhdl-basic-offset vhdl-include-group-comments no-init vhdl-include-port-comments vhdl-auto-align] 7 (#$ . 371009)])
#@22 Paste a port clause.
(defalias 'vhdl-port-paste-port #[nil "\306 \3078\310\211\211\211
\205\261`\311\312!\210\204)\313c\210\\j\210i
\203\247
@\314>\203@\315\316	8\f\"\210	A@\203M	A@\317\261\210	@\n\203e\n@c\210\nA\211\203P\320c\210\202P\321c\210\307	8\203u\307	8\317\261\210\322	8c\210
A\204\202\323c\210\324c\210\203\227\325	8\203\227\326\325	8\327\"\210
A\211\203+\313c\210\fj\210\202+\205\261\330`\331#.\207" [vhdl-port-list port names start list-margin port-list current-indentation 2 nil vhdl-insert-keyword "PORT (" "\n" (decl always) vhdl-paste-group-comment 5 " " ", " " : " 3 ")" ";" 4 vhdl-comment-insert-inline t vhdl-align-region-groups 1 margin vhdl-argument-list-indent vhdl-basic-offset vhdl-include-group-comments vhdl-include-port-comments vhdl-auto-align] 7 (#$ . 371869)])
#@46 Paste as an entity or component declaration.
(defalias 'vhdl-port-paste-declaration #[(kind &optional no-indent) "\204\306 \210\307 	@\310\f\311=\203\312\202\313!\210\nc\210\f\311=\204*\314\315!\204.\310\316!\210	A@\203R\317c\210
\320>\203F\f\311=\203F\317c\210\\j\210\321\f\322=!\210\323	8\203p\317c\210
\324>\203j\f\311=\203j\317c\210\\j\210\325 \210\317c\210
\326>\203\205\f\311=\203\205\317c\210j\210\310\327!\210\f\311=\203\244\314\315!\204\234\310\330!\210\331\n\261\210\202\263\310\332!\210\314\315!\204\263\331\n\261\210\333c*\207" [no-indent vhdl-port-list name margin kind vhdl-insert-empty-lines indent-according-to-mode current-indentation vhdl-insert-keyword entity "ENTITY " "COMPONENT " vhdl-standard-p 87 " IS" "\n" (unit all) vhdl-port-paste-generic component 2 (unit all) vhdl-port-paste-port (unit all) "END" " ENTITY" " " " COMPONENT" ";" vhdl-basic-offset] 3 (#$ . 372712)])
#@33 Paste as an entity declaration.
(defalias 'vhdl-port-paste-entity #[(&optional no-indent) "\204\302\303!\207\304\305@\"\210\306\307	\"\210\304\310@\"\207" [vhdl-port-list no-indent error "ERROR:  No port read" message "Pasting port as entity \"%s\"..." vhdl-port-paste-declaration entity "Pasting port as entity \"%s\"...done"] 3 (#$ . 373646) nil])
#@35 Paste as a component declaration.
(defalias 'vhdl-port-paste-component #[(&optional no-indent) "\204\302\303!\207\304\305@\"\210\306\307	\"\210\304\310@\"\207" [vhdl-port-list no-indent error "ERROR:  No port read" message "Pasting port as component \"%s\"..." vhdl-port-paste-declaration component "Pasting port as component \"%s\"...done"] 3 (#$ . 374007) nil])
#@25 Paste as a generic map.
(defalias 'vhdl-port-paste-generic-map #[(&optional secondary no-constants) "\204\306 \210\307 \310\211\211	A@\n\205\376`\311\312!\210\204`\n\205\376 \2034\n@@@\202<\313\n@8\206<\314c\210\nA\211\203I\315\202J\316c\210\n\204$\203$\313	8\204$\317c\210\202$!\204o\320c\210\"\\j\210i\n\203\363\n@#\321=\203\206\322\3238
\"\210@@\324 \203\225@@\202\234\3138\206\234\325\261\210\nA\211\203\252\326\202\253\316c\210\n\204\276\203\276\313	8\204\276\317c\210$\204\316%\203\346\3278\203\346\330$\205\332\331A@\332Q%\205\342\3278P\333\"\210\n\203q\320c\210
j\210\202q&\205\376\334\f`\335\333$-\207" [secondary vhdl-port-list generic-list generic start list-margin indent-according-to-mode current-indentation nil vhdl-insert-keyword "GENERIC MAP (" 2 " " ", " ")" ";" "\n" always vhdl-paste-group-comment 4 " => " "" "," 3 vhdl-comment-insert-inline "[" "] " t vhdl-align-region-groups 1 margin vhdl-association-list-with-formals no-constants vhdl-argument-list-indent vhdl-basic-offset vhdl-include-group-comments vhdl-include-type-comments vhdl-include-port-comments vhdl-auto-align] 6 (#$ . 374382) nil])
#@22 Paste as a port map.
(defalias 'vhdl-port-paste-port-map #[nil "\306 \307\211\211\3108	\205
`\311\312!\210\"\204;	\205
\313#	@@@\"c\210	A\211\2035\314\2026\315c\210\202$\204I\316c\210
%\\j\210i	\203\371	@&\317=\203`\320\321\n8\f\"\210\n@@\322\261\210\313#\n@@\"c\210	A\211\203{\323\202|\324c\210'\203\211\310\n8\204\231(\204\231)\203\354\325\n8\203\354\326'\203\265(\203\265\327\330\331\310\n8\332P\"\333\n8\334R\202\340'\203\314\310\n8\203\314\330\335\327\310\n8\334Q\"\202\340'\203\325\336\202\340(\205\340\327\333\n8\334Q)\205\350\325\n8P\337\"\210	\203K\316c\210\fj\210\202K*\205
\340`\341#-\207" [vhdl-port-list port-list port start list-margin margin current-indentation nil 2 vhdl-insert-keyword "PORT MAP (" vhdl-replace-string ", " ")" "\n" always vhdl-paste-group-comment 5 " => " "," ");" 4 vhdl-comment-insert-inline "[" format "%-4s" " " 3 "] " "%-6s" "      " t vhdl-align-region-groups 1 vhdl-association-list-with-formals vhdl-actual-port-name vhdl-argument-list-indent vhdl-basic-offset vhdl-include-group-comments vhdl-include-direction-comments vhdl-include-type-comments vhdl-include-port-comments vhdl-auto-align] 7 (#$ . 375578)])
#@28 Paste as an instantiation.
(defalias 'vhdl-port-paste-instance #[(&optional name no-indent title) "\204\306\307!\207\310 \210\n\204\311 \210\312 \f\203!\fc\210\202g
A\313\232\203/\314\315!\202g\316\317
A\"\203`\320'\212\321\322
@\"'\"eb\210\323\f\324\325#)\203Y'T'\202:\fc\210)\202g\322
@\"c\210\326\327\f\"\210\330c\210(\203\203\212\331 \210)j\210\332\f\333\261\210)\334 \204\217@c\210\202\233\335\336!\210\337 \340@\261\210A@\203\257\341c\210)\\j\210\342\325\211\"\210\3438\203\301\341c\210)\\j\210\344 \210A@\204\320\3438\204\320\345c\210\326\346\f\"\210)	\211)\207" [vhdl-port-list orig-vhdl-port-list no-indent margin name vhdl-instance-name error "ERROR:  No port read" vhdl-port-flatten indent-according-to-mode current-indentation "" vhdl-template-field "instance name" string-match "%d" 1 format vhdl-replace-string vhdl-re-search-forward nil t message "Pasting port as instantiation \"%s\"..." ": " beginning-of-line "-- instance \"" "\"\n" vhdl-use-direct-instantiation vhdl-insert-keyword "ENTITY " vhdl-work-library "." "\n" vhdl-port-paste-generic-map 2 vhdl-port-paste-port-map ";" "Pasting port as instantiation \"%s\"...done" n title vhdl-basic-offset] 4 (#$ . 376796) nil])
#@30 Paste generics as constants.
(defalias 'vhdl-port-paste-constants #[(&optional no-indent) "\204\306\307!\207\310\311!\210\312 \210\n\204\313 \210\314 \315\211\211A@\203\231`\203\215@ \316>\203D\317\320
8\"\210\321\322!\210
@\211\203.\f@c\210\323
A@\261\210\324
8\203g\325\324
8\261\210\326c\210!\203|\327
8\203|\330\327
8\331\"\210A\211\203.\332c\210j\210\202.\"\203\231\333`\334#\210-\310\335!\210	\211)\207" [vhdl-port-list orig-vhdl-port-list no-indent generic-list name generic error "ERROR:  No port read" message "Pasting port as constants..." vhdl-port-flatten indent-according-to-mode current-indentation nil (decl always) vhdl-paste-group-comment 4 vhdl-insert-keyword "CONSTANT " " : " 2 " := " ";" 3 vhdl-comment-insert-inline t "\n" vhdl-align-region-groups 1 "Pasting port as constants...done" start margin vhdl-include-group-comments vhdl-include-port-comments vhdl-auto-align] 6 (#$ . 378040) nil])
#@34 Paste ports as internal signals.
(defalias 'vhdl-port-paste-signals #[(&optional initialize no-indent) "\204\306\307!\207\310\311!\210	\204\312 \210\313 \314\211\211\31581\n\203-
`\n\203\"
\n@2\316>\203=\317\320\f81\"\210\fA@\203M\fA@\321\261\210\202Q\322\323!\210\f@\203m\3243@\"c\210A\211\203T\325c\210\202T\326\327\f8\261\2104\203\316\315\f8\203\316\315\f8\226\330\232\203\316\331\332\333\327\f8\"\203\226\334\202\313\332\335\327\f8\"\203\243\334\202\313\332\336\327\f8\"\203\260\334\202\313\332\337\327\f8\"\203\275\340\202\313\332\341\327\f8\"\203\312\342\202\313\343\261\210\344c\2105\203\334\315\f8\204\3476\203
\345\f8\203
\3465\203\377\315\f8\203\377\347\350\351\315\f8\352Q\"\202
5\205
\3536\205

\345\f8P\354\"\210\nA\211\203'\355c\2101j\210\202'7\203-
\356
`\357#\210-\310\360!\207" [vhdl-port-list no-indent port-list names port start error "ERROR:  No port read" message "Pasting port as signals..." indent-according-to-mode current-indentation nil 2 (decl always) vhdl-paste-group-comment 5 " " vhdl-insert-keyword "SIGNAL " vhdl-replace-string ", " " : " 3 "IN" " := " string-match "integer" "0" "natural" "positive" "real" "0.0" "(.+)" "(others => '0')" "'0'" ";" 4 vhdl-comment-insert-inline format "%-6s" "[" "] " "      " t "\n" vhdl-align-region-groups 1 "Pasting port as signals...done" margin vhdl-include-group-comments vhdl-actual-port-name initialize vhdl-include-direction-comments vhdl-include-port-comments vhdl-auto-align] 7 (#$ . 379006) nil])
#@40 Paste ports as signal initializations.
(defalias 'vhdl-port-paste-initializations #[(&optional no-indent) "\204\306\307!\207\310\311!\210\312 \210\n\204\313 \210\314 \315\211\211\3168\"#\203\267`\"\203\253@\316
8\226\317\232\203\220
@@\320$\f\"c\210\321\322\323\324
8\"\203W\325\202\214\322\326\324
8\"\203d\325\202\214\322\327\324
8\"\203q\325\202\214\322\330\324
8\"\203~\331\202\214\322\332\324
8\"\203\213\333\202\214\334\335\261\210A\211\203.\316@8\226\317\232\203.\336c\210#j\210\202.%\203\267\337\"`\340#\210-\310\341!\210	\211)\207" [vhdl-port-list orig-vhdl-port-list no-indent port-list name port error "ERROR:  No port read" message "Pasting port as initializations..." vhdl-port-flatten indent-according-to-mode current-indentation nil 2 "IN" vhdl-replace-string " <= " string-match "integer" 3 "0" "natural" "positive" "real" "0.0" "(.+)" "(others => '0')" "'0'" ";" "\n" vhdl-align-region-groups 1 "Pasting port as initializations...done" start margin vhdl-actual-port-name vhdl-auto-align] 7 (#$ . 380549) nil])
#@34 Paste as a bare-bones testbench.
(defalias 'vhdl-port-paste-testbench #[nil "\204\306\307!\207\310\311	@\"p\312\211\211\211\211\211\211@ABCDEF\313=\204u\311GD\310#\314\315\316 !Q@\317@!\203p\320\321@\322Q!\203\\\323@!\210\324 \210\325\312!\210\202uF\326=\203i\312@\202u\306\327!\210\202u\323@!\210F\326=\203\201@\203\341H\203\224\330\331@\332Q!\210db\210\202\232\333 \210\334c\210I\203\253\335 \210\334c\210\333 \210\334c\210\336\337!\210Dc\210\336\340!\210J\341>\203\301\342c\210\342c\210\336\343!\210\344\345!\204\322\336\337!\210D\346\261\210\334c\210\333 \210\342c\210KA\347\232\203\362\350\351\312L#\202\370\311K@\"B\352\353DB#\210F\326=\204
\342c\210\202Z
p\311MD\354BQ\310#\314\315\316 !Q\317
!\2036
\320\321
\322Q!\2046
\306\327!\210\323
!\210\324 \210\325\312!\210H\203T
\330\355@\332Q!\210db\210\202Z
\333 \210\334c\210\336\356!\210Bc\210\336\357!\210Dc\210\336\340!\210\334c\210Nj\210\360 \204\205
\361\310!\210\334c\210Nj\210A@\203\235
\362c\210Nj\210\363\310!\210\334c\210Nj\210\364c\210Nj\210\365O\310\"\210\342c\210P\347\232\204\303
\342c\210`\366P!\210\367\n`\"\210`\334c\210\333 \210\342c\210Q\203\311RD\354BQ\"A\342c\210\336\370!\210Ac\210\336\357!\210Dc\210\336\371!\210Nj\210\336\372!\210B\342\261\210Nj\210\336\373!\210\336\343!\210A\374\261\210\333 \210\342c\210\nb\210\375\344\345!?\205(\376B\377\310$\210\201Uc\210Nj\210\201V\311S@\"\310\"\210\342c\210T\347\232\204\\\342c\210`\366T!\210\367\n`\"\210\342c\210Nj\210F\313=\204\200p\f\203x\fq\210\201W \210q\210\201W \210\352\201X\201Y\201ZDB#@\205\235\201Y\201[@\"
\205\251\201Y\201[
\"Q\".\n\207" [vhdl-port-list vhdl-testbench-entity-name position arch-buffer ent-buffer arch-file-name error "ERROR:  No port read" t vhdl-replace-string nil none "." file-name-extension buffer-file-name file-exists-p y-or-n-p "File \"" "\" exists; overwrite? " find-file erase-buffer set-buffer-modified-p separate "ERROR:  Pasting port as testbench...aborted" vhdl-template-header "Testbench for design \"" "\"" vhdl-comment-display-line "\n\n" vhdl-template-package-std-logic-1164 vhdl-insert-keyword "ENTITY " " IS" (unit all) "\n" "END " vhdl-standard-p 87 ";" "" read-from-minibuffer "architecture name: " message "Pasting port as testbench \"%s(%s)\"..." " " "Testbench architecture for design \"" "ARCHITECTURE " " OF " vhdl-use-direct-instantiation vhdl-port-paste-component "-- component generics\n" vhdl-port-paste-constants "-- component ports\n" vhdl-port-paste-signals vhdl-insert-string-or-file vhdl-indent-region "CONFIGURATION " " IS\n" "FOR " "END FOR;\n" ";\n\n" vhdl-template-begin-end "ARCHITECTURE" 0 ent-file-name config-name arch-name source-buffer ent-name case-fold-search vhdl-testbench-create-files vhdl-testbench-entity-file-name vhdl-testbench-include-header vhdl-testbench-include-library vhdl-insert-empty-lines vhdl-testbench-architecture-name vhdl-minibuffer-local-map vhdl-testbench-architecture-file-name vhdl-basic-offset vhdl-testbench-initialize-signals vhdl-testbench-declarations vhdl-testbench-include-configuration vhdl-testbench-configuration-name vhdl-testbench-dut-name vhdl-testbench-statements "-- component instantiation\n" vhdl-port-paste-instance save-buffer "%s" format "Pasting port as testbench \"%s(%s)\"...done" "\n  File created: \"%s\""] 10 (#$ . 381627) nil])
#@52 Variable to hold last subprogram interface parsed.
(defvar vhdl-subprog-list nil (#$ . 385035))
#@63 Indicates whether an subprogram interface has been flattened.
(defvar vhdl-subprog-flattened nil (#$ . 385137))
#@68 Flatten interface list so that only one parameter exists per line.
(defalias 'vhdl-subprog-flatten #[nil "\204\306\307!\207\310\311!\210\3128\313\211\211\211\211\203A
@\211@\211\203:	@CAB\314\f\nC\"	A\211\204&
A\211\204@A@\f\3158\3168\3178\257\320\310\321!-\207" [vhdl-subprog-list names new-subprog old-subprog new-subprog-list old-subprog-list error "ERROR:  No subprogram interface has been read" message "Flattening subprogram interface..." 2 nil append 3 4 5 t "Flattening subprogram interface...done" vhdl-subprog-flattened] 8 (#$ . 385255) nil])
#@60 Get interface information from a subprogram specification.
(defalias 'vhdl-subprog-copy #[nil "\212\306\211\211\211\211\211\211\211\211\211\211\211\211\211\211\211\307\310 \306\211\211 !\"\311#!\210\312\313!\203}\313  \314 @ A\"\211 \203} @\315\316!>\203tB\317\315\306#\210 A\211 \204X\320\216\321\322\215.\203\222\323!\202\243\n	\257$\306\211%.\207" [return-group-comment return-comment return-type group-comment comment init nil t syntax-table set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) parse (byte-code "`\306\210\307\310!\203\311\225b\210\312\313\306\314#\203+\311\225b\203+\212\315u\210\316 \210`X)\2040\317\320\321\"\210\322\323!\324\325!\203>\326\202?\327\324\330!?\331\332	\"\210\333 \206U\334\335\314\"\204\347
\334\336\314\"\205d\322\337!\334\340!\210\322\337!C6\334\341\314\"\203\203\3426\322\337!C\"6\202o\334\343!\210\334\344\314\"\205\221\322\337!7\334\345!\210\322\337!8\3069\307\346!\203\2768\347`\316 \210`\"\334\350\314\"\205\270\322\337!Q8\202\2378\203\333\351\3528\"\203\3338\325\224\306O98\311\337\224O8\351\3538\"\2108\311\337\225O8\306:\334\354\314\"\203
\334\355!\210\322\337!:\307\346!\203
:\347`\316 \210`\"\334\355\314\"\205
\322\337!Q:\202\374:\203;
\351\352:\"\203;
:\325\224\306O9:\311\337\224O:\356 \210\357\306w\2109\204P
\334\360\314\"\205N
\322\337!9\356 \210\334\361\314\"9\204i
\334\360\314\"\205g
\322\337!9\333 ;\334\362!\210\324\363!\203\273
\334\364!\210\322\337!\211<\203\234
\351\352<\"\203\234
<\325\224\306O=<\311\337\224O<\351\353<\"\210<\311\337\225O<=\204\273
\334\360\314\"\205\271
\322\337!=9\204\314
\334\360\314\"\205\312
\322\337!9\342>6
78:9\f\257C\">\333 \202V\331\365	\"\210\306\207" [pos name kind end-of-list group-comment object nil looking-at "[ 	\n
\f]*\\((\\|;\\|is\\>\\)" 0 re-search-backward "^\\s-*\\(\\(procedure\\)\\|\\(\\(pure\\|impure\\)\\s-+\\)?function\\)\\s-+\\(\"?\\w+\"?\\)[ 	\n
\f]*\\(\\((\\)\\|;\\|is\\>\\)" t -1 forward-sexp throw parse "ERROR:  Not within a subprogram specification" match-string-no-properties 5 match-string 2 procedure function 7 message "Reading interface of subprogram \"%s\"..." vhdl-parse-group-comment vhdl-parse-string ")[ 	\n
\f]*\\(;\\|\\(is\\|return\\)\\>\\)" "\\(constant\\|signal\\|variable\\|file\\|quantity\\|terminal\\)[ 	\n
\f]*" 1 "\\(\\\\[^\\]+\\\\\\|\\w+\\)[ 	\n
\f]*" ",[ 	\n
\f]*\\(\\\\[^\\]+\\\\\\|\\w+\\)[ 	\n
\f]*" append ":[ 	\n
\f]*" "\\(in\\|out\\|inout\\|buffer\\|linkage\\)[ 	\n
\f]+" "\\([^():;\n]+\\)" "(" buffer-substring-no-properties "\\([^():;\n]*\\)" string-match "\\(\\s-*--\\s-*\\)\\(.*\\)" "\\(\\(\\s-*\\S-+\\)+\\)\\s-*" ":=[ 	\n
\f]*" "\\([^();\n]*\\)" vhdl-forward-syntactic-ws " 	" "--\\s-*\\([^\n]*\\)" ")\\s-*" "\\(;\\|\\(is\\|\\(return\\)\\)\\>\\)\\s-*" 3 "[ 	\n
\f]*\\(.+\\)[ 	\n
\f]*\\(;\\|is\\>\\)\\s-*" "Reading interface of subprogram \"%s\"...done" names direct type comment init return-group-comment return-type return-comment param-list] 10) error type direct names object param-list kind name end-of-list pos parse-error overlay overlay-intangible-list overlay-all-list current-syntax-table case-fold-search vhdl-mode-ext-syntax-table vhdl-subprog-list vhdl-subprog-flattened] 17 (#$ . 385844) nil])
#@38 Paste as a subprogram specification.
(defalias 'vhdl-subprog-paste-specification #[(kind) "\306 \210i\3078\310\211\211\211(\311A@\312=\203\313\202 \314!\210@c\210
\204>)\315=\2037\316c\210\202M
\311\317!\210\202M
`\320c\210*\204R\321c\210(+\\j\210i
\203\372
@,)\322D>\203l\323\324	8\f\"\210	A@\203y	A@\325\261\210	@\n\203\221\n@c\210\nA\211\203|\326c\210\202|\327c\210\307	8\203\241\307	8\325\261\210\330	8c\210\331	8\203\263\332\331	8\261\210
A\203\276\316c\210\202\330\333c\210\3308\204\330)\315=\203\324\316c\210\202\330\311\317!\210-\203\352\334	8\203\352\335\334	8\336\"\210
A\211\203T\321c\210\fj\210\202T\3308\203A
\321c\210\fj\210,)\322D>\203
\323\3348\f\"\210\337\3308\261\210)\315=\203+
\316c\210\202/
\311\317!\210-\203A
\3318\203A
\335\3318\336\"\210.\203M
\340`\341\336$\210)\342=\205q
\321c\210\343\344\345!?\205l
A@\312=\203k
\346\202l
\347@(#.\207" [vhdl-subprog-list param names start list-margin param-list indent-according-to-mode 2 nil vhdl-insert-keyword procedure "PROCEDURE " "FUNCTION " decl ";" " is" " (" "\n" always vhdl-paste-group-comment 6 " " ", " " : " 3 4 " := " ")" 5 vhdl-comment-insert-inline t "return " vhdl-align-region-groups 1 body vhdl-template-begin-end vhdl-standard-p 87 "PROCEDURE" "FUNCTION" margin kind vhdl-argument-list-indent vhdl-basic-offset vhdl-include-group-comments vhdl-include-port-comments vhdl-auto-align] 7 (#$ . 389411)])
#@36 Paste as a subprogram declaration.
(defalias 'vhdl-subprog-paste-declaration #[nil "\204\301\302!\207\303\304@\"\210\305\306!\210\303\307@\"\207" [vhdl-subprog-list error "ERROR:  No subprogram interface read" message "Pasting interface as subprogram declaration \"%s\"..." vhdl-subprog-paste-specification decl "Pasting interface as subprogram declaration \"%s\"...done"] 3 (#$ . 390870) nil])
#@29 Paste as a subprogram body.
(defalias 'vhdl-subprog-paste-body #[nil "\204\301\302!\207\303\304@\"\210\305\306!\210\303\307@\"\207" [vhdl-subprog-list error "ERROR:  No subprogram interface read" message "Pasting interface as subprogram body \"%s\"..." vhdl-subprog-paste-specification body "Pasting interface as subprogram body \"%s\"...done"] 3 (#$ . 391276) nil])
#@29 Paste as a subprogram call.
(defalias 'vhdl-subprog-paste-call #[nil "\204\306\307!\207\310\211\211\211\211\311 \210\3128\313 \210\314 \315\316@\"\210@c\210
\2046\317c\210\202\236`\320c\210\204I\321c\210\f\\j\210i
\203\223
@ \322=\203`\323\324\n8\"\210\n@@\325\261\210
A\211\203r\326\202s\327c\210!\203\206\330\n8\203\206\331\330\n8!\210
\203K\321c\210j\210\202K\"\203\236\332	`\333#\210\315\334@\"\210\211.\207" [vhdl-subprog-list start param list-margin margin param-list error "ERROR:  No subprogram interface read" nil vhdl-subprog-flatten 2 indent-according-to-mode current-indentation message "Pasting interface as subprogram call \"%s\"..." ";" " (" "\n" always vhdl-paste-group-comment 6 " => " "," ");" 5 vhdl-comment-insert-inline vhdl-align-region-groups 1 "Pasting interface as subprogram call \"%s\"...done" orig-vhdl-subprog-list vhdl-argument-list-indent vhdl-basic-offset vhdl-include-group-comments vhdl-include-port-comments vhdl-auto-align] 7 (#$ . 391654) nil])
(defvar vhdl-expand-upper-case nil)
#@54 Try expanding abbreviations from `vhdl-abbrev-list'.
(defalias 'vhdl-try-expand-abbrev #[(old) "\2042\306\307 `\"\210	\310\211\203.@;\203\"\311\312\fP@\"\203'@\nBA\211\204\n\237*
\203W
@;\203F\313
@\314#\203W
@;\204P
@
A\211\2046
\204d\203b\315 \210\310\207\316\203p
@\226\202r
@\314\"\210
A\314\207" [old vhdl-abbrev-list sel-abbrev-list abbrev-list he-search-string he-expand-list he-init-string he-dabbrev-beg nil string-match "^" he-string-member t he-reset-string he-substitute-string he-tried-table vhdl-expand-upper-case] 5 (#$ . 392725)])
#@132 Also looks at the word before `(' in order to better match parenthesized
expressions (e.g. for index ranges of types and signals).
(defalias 'vhdl-he-list-beg #[nil "\212\300\301\302\217\210`)\207" [nil (byte-code "\300\301!\210\302\303!\207" [backward-up-list 1 skip-syntax-backward "w_"] 2) ((error))] 3 (#$ . 393313)])
(byte-code "\301\300!\203\n\204\302\303\304\"\210\301\207" [viper-mode boundp defalias he-list-beg vhdl-he-list-beg] 3)
#@141 Try to expand text before point, using the following functions: 
try-expand-dabbrev, try-expand-dabbrev-all-buffers, vhdl-try-expand-abbrev
(defalias 'vhdl-expand-abbrev #[(arg) "\303\304\305\n!*\207" [hippie-expand-verbose hippie-expand-try-functions-list arg (try-expand-dabbrev try-expand-dabbrev-all-buffers vhdl-try-expand-abbrev) nil hippie-expand] 2 (#$ . 393766) "P"])
#@111 Try to expand text before point, using the following functions: 
try-expand-list, try-expand-list-all-buffers
(defalias 'vhdl-expand-paren #[(arg) "\303\304\305\n!*\207" [hippie-expand-verbose hippie-expand-try-functions-list arg (try-expand-list try-expand-list-all-buffers) nil hippie-expand] 2 (#$ . 394152) "P"])
#@109 Convert all words matching WORD-REGEXP in region to lower or upper case,
depending on parameter UPPER-CASE.
(defalias 'vhdl-fix-case-region-1 #[(beg end upper-case word-regexp &optional count) "\306\307\310\311 \306\211\211\312!\210\313\314!\203E\314 \315\f@\fA\"\211\203E\f@\316\317\n!>\203>\nB\320\n\316\306#\210\fA\211\204)\321\216\212b\210\322  b\210\323!\310#\203\254\324 \204s\"\203o\325\326!\210\202s\327\326!\210#\203T$\203T%\204T$\330 A@ZW\203T\331\332#\333_` Z\333_ Z\245\\\334#\210\330 A@\202Tb.	\207" [last-update case-replace overlay overlay-intangible-list overlay-all-list current-syntax-table nil 0 t syntax-table set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) point-marker re-search-forward vhdl-in-literal upcase-word -1 downcase-word current-time message "Fixing case... (%2d%s)" 20 "%" case-fold-search vhdl-mode-ext-syntax-table end beg word-regexp upper-case count vhdl-progress-interval noninteractive] 7 (#$ . 394478)])
#@136 Convert all VHDL words in region to lower or upper case, depending on
options vhdl-upper-case-{keywords,types,attributes,enum-values}.
(defalias 'vhdl-fix-case-region #[(beg end &optional arg) "\306	\n\307%\210\306	\f
\310%\210\306	\311P\312%\210\306	\313%\210\306	\314%\210\2058\315\316!\207" [beg end vhdl-upper-case-keywords vhdl-keywords-regexp vhdl-upper-case-types vhdl-types-regexp vhdl-fix-case-region-1 0 1 "'" 2 3 4 message "Fixing case...done" vhdl-upper-case-attributes vhdl-attributes-regexp vhdl-upper-case-enum-values vhdl-enum-values-regexp vhdl-upper-case-constants vhdl-constants-regexp vhdl-progress-interval] 6 (#$ . 395723) "r\nP"])
#@136 Convert all VHDL words in buffer to lower or upper case, depending on
options vhdl-upper-case-{keywords,types,attributes,enum-values}.
(defalias 'vhdl-fix-case-buffer #[nil "\300ed\"\207" [vhdl-fix-case-region] 3 (#$ . 396405) nil])
#@55 Convert word after cursor to upper case if necessary.
(defalias 'vhdl-fix-case-word #[(&optional arg) "\212\203\306v\210\307\310 p\311\216\312\f!\210
\203$\313!\203$\314\315!\210\2034\313!\2034\314\315!\210\203D\313!\203D\314\315!\210\203T\313!\203T\314\315!\210\205c\313!\205c\314\315!-\207" [arg case-fold-search #1=#:buffer #2=#:table vhdl-mode-ext-syntax-table vhdl-upper-case-keywords -1 t syntax-table ((byte-code "rq\210\302	!\210)\302\207" [#1# #2# set-syntax-table] 2)) set-syntax-table looking-at upcase-word 1 vhdl-keywords-regexp vhdl-upper-case-types vhdl-types-regexp vhdl-upper-case-attributes vhdl-attributes-regexp vhdl-upper-case-enum-values vhdl-enum-values-regexp vhdl-upper-case-constants vhdl-constants-regexp] 2 (#$ . 396644) "p"])
#@54 Return the line number of the line containing point.
(defalias 'vhdl-current-line #[nil "\214~\210\300e\301 \"T)\207" [count-lines point-at-bol] 3 (#$ . 397440)])
#@21 Delete entire line.
(defalias 'vhdl-line-kill-entire #[(&optional arg) "\301 \210\302\206	\303!\207" [arg beginning-of-line kill-line 1] 2 (#$ . 397609) "p"])
#@20 Kill current line.
(defalias 'vhdl-line-kill #[(&optional arg) "\301!\207" [arg vhdl-line-kill-entire] 2 (#$ . 397776) "p"])
#@20 Copy current line.
(defalias 'vhdl-line-copy #[(&optional arg) "\212\302 	\206	\303y\210\304`\"*\207" [position arg point-at-bol 1 copy-region-as-kill] 3 (#$ . 397908) "p"])
#@19 Yank entire line.
(defalias 'vhdl-line-yank #[nil "\300 \210\301 \207" [beginning-of-line yank] 1 (#$ . 398091) nil])
#@29 Hippie-expand current line.
(defalias 'vhdl-line-expand #[(&optional prefix-arg) "\304\305!\210\306\307\310\311!+\207" [hippie-expand-try-functions-list case-replace case-fold-search prefix-arg require hippie-exp t nil (try-expand-line try-expand-line-all-buffers) hippie-expand] 3 (#$ . 398215) "P"])
#@39 Interchange this line with next line.
(defalias 'vhdl-line-transpose-next #[(&optional arg) "\301y\210\302\206	\301!\210\303y\207" [arg 1 transpose-lines -1] 2 (#$ . 398527) "p"])
#@43 Interchange this line with previous line.
(defalias 'vhdl-line-transpose-previous #[(&optional arg) "\301y\210\302\206	\303[!\210\304y\207" [arg 1 transpose-lines 0 -1] 2 (#$ . 398715) "p"])
#@29 Open a new line and indent.
(defalias 'vhdl-line-open #[nil "\300\210\301 \207" [0 newline-and-indent] 1 (#$ . 398914) nil])
#@106 Join lines.  That is, call `delete-indentation' with `fill-prefix' so that
it works within comments too.
(defalias 'vhdl-delete-indentation #[nil "\301\302 )\207" [fill-prefix "-- " delete-indentation] 1 (#$ . 399047) nil])
#@45 Move forward to next line with same indent.
(defalias 'vhdl-forward-same-indent #[nil "`\302 \303\304!\210m\204!\305\306!\204\302 V\203!\303\304!\210\202	\302 U\203-\307 \2025\310\311!\210	b\210\312*\207" [indent pos current-indentation beginning-of-line 2 looking-at "^\\s-*\\(--.*\\)?$" back-to-indentation message "No following line with same indent found in this block" nil] 2 (#$ . 399278) nil])
#@50 Move backward to previous line with same indent.
(defalias 'vhdl-backward-same-indent #[nil "`\302 \303\304!\210o\204!\305\306!\204\302 V\203!\303\304!\210\202	\302 U\203-\307 \2025\310\311!\210	b\210\312*\207" [indent pos current-indentation beginning-of-line 0 looking-at "^\\s-*\\(--.*\\)?$" back-to-indentation message "No preceding line with same indent found in this block" nil] 2 (#$ . 399696) nil])
#@27 Get some file statistics.
(defalias 'vhdl-statistics-buffer #[nil "\306\211\211\211\211\307ed\"\212eb\210\310\311\312\313#\203.\314\315!\203(\315\225b\210\202
T\202eb\210m\204E\316\317!\204>\fT\320\321!\210\2021eb\210\310\322\312\313#\203r`d=\204r\314\315!\203c\315\225b\210\202HT`d=\204H\312u\210\202Heb\210\310\323\312\313#\203\220\314\315!\203\212\315\225b\210\202u\nT\202ueb\210\310\324\312\313#\203\256\314\315!\203\250\315\225b\210\202\223	T\202\223)\325\326\327 
\f\n	&\210?\205\304\330 .\207" [no-lines no-comments no-comm-lines no-empty-lines no-code-lines no-stats 0 count-lines re-search-forward "\\(--.*\n\\|\"[^\"\n]*[\"\n]\\)\\|;" nil t match-string 1 looking-at "^\\s-*\\(--.*\\)?$" beginning-of-line 2 "^\\s-*$" "^\\s-*--.*" "--.*" message "\nFile statistics: \"%s\"\n---------------------\n# statements    : %5d\n# code lines    : %5d\n# empty lines   : %5d\n# comment lines : %5d\n# comments      : %5d\n# total lines   : %5d\n" buffer-file-name vhdl-show-messages vhdl-emacs-21] 9 (#$ . 400120) nil])
#@63 Like `re-search-forward', but does not match within literals.
(defalias 'vhdl-re-search-forward #[(regexp &optional bound noerror count) "\305\212\306	\n\f$\211\203\307 \204)\203b\210)\207" [pos regexp bound noerror count nil re-search-forward vhdl-in-literal] 5 (#$ . 401188)])
#@64 Like `re-search-backward', but does not match within literals.
(defalias 'vhdl-re-search-backward #[(regexp &optional bound noerror count) "\305\212\306	\n\f$\211\203\307 \204)\203b\210)\207" [pos regexp bound noerror count nil re-search-backward vhdl-in-literal] 5 (#$ . 401485)])
#@30 Set current project to NAME.
(defalias 'vhdl-set-project #[(name) "\303\232\203\304\305\306!\210\202'\307\n\"\203 \305\310\"\210\202'\311\312\313\"!\210\314 \207" [name vhdl-project vhdl-project-alist "" nil message "Current VHDL project: None" assoc "Current VHDL project: \"%s\"" vhdl-warning format "Unknown VHDL project: \"%s\"" vhdl-speedbar-update-current-project] 4 (#$ . 401785) (list (let ((completion-ignore-case t)) (completing-read "Project name: " vhdl-project-alist nil t)))])
#@44 Set current project as default on startup.
(defalias 'vhdl-set-default-project #[nil "\301\300\"\210\302 \207" [vhdl-project customize-set-variable customize-save-customized] 3 (#$ . 402294) nil])
#@66 Set current project to NAME or unset if NAME is current project.
(defalias 'vhdl-toggle-project #[(name token indent) "\302	\232\203\303\202\f!\207" [name vhdl-project vhdl-set-project ""] 3 (#$ . 402498)])
#@42 Write project setup for current project.
(defalias 'vhdl-export-project #[(file-name) "\305!p\306\307!!\204\310\307!\311\"\210\312!\204\"\313\314\"\202[\315\311\211#q\210\316 \210\317\320\321!\322\n\323\324\325\326\327\330!\331 \332\333\334\335\336\337\261\210\340\341\f\"p\"\210\342c\210\343 \210\344p!\210	q)\207" [file-name orig-buffer vhdl-version vhdl-project vhdl-project-alist abbreviate-file-name file-exists-p file-name-directory make-directory t file-writable-p error "ERROR:  File not writable: \"%s\"" find-file-noselect erase-buffer ";; -*- Emacs-Lisp -*-\n\n" ";;; " file-name-nondirectory " - project setup file for Emacs VHDL Mode " "\n\n" ";; Project : " "\n" ";; Saved   : " format-time-string "%Y-%m-%d %T " user-login-name "\n\n\n" ";; project name\n" "(setq vhdl-project \"" "\")\n\n" ";; project setup\n" "(aput 'vhdl-project-alist vhdl-project\n'" pp aget ")\n" save-buffer kill-buffer] 19 (#$ . 402716) (let ((name (vhdl-resolve-env-variable (vhdl-replace-string (cons "\\(.*\\) \\(.*\\)" (car vhdl-project-file-name)) (concat (subst-char-in-string 32 95 (or (vhdl-project-p) (error "ERROR:  No current project"))) " " (user-login-name)))))) (list (read-file-name "Write project file: " (if (file-name-absolute-p name) (progn "")) nil nil name)))])
#@45 Read project setup and set current project.
(defalias 'vhdl-import-project #[(file-name &optional auto not-make-current) "\301!\205\n\302\303\304\217\207" [file-name file-exists-p nil (byte-code "\306\n!\210\307\310#G\311U\204\312\303\"\210\313\314!\210\f\203 	\315 \210\316 \210\f?\2058\317\320
\2036\321\2027\314#)\207" [vhdl-project current-project file-name vhdl-project-alist not-make-current auto load-file aget t 10 adelete error "" vhdl-update-mode-menu vhdl-speedbar-refresh message "Current VHDL project: \"%s\"%s" " (auto-loaded)"] 4) ((error (byte-code "\301\302\303\"!\207" [file-name vhdl-warning format "ERROR:  Invalid project setup file: \"%s\""] 4)))] 3 (#$ . 404012) (let ((name (vhdl-resolve-env-variable (vhdl-replace-string (cons "\\(.*\\) \\(.*\\)" (car vhdl-project-file-name)) (concat #1="" " " (user-login-name)))))) (list (read-file-name "Read project file: " (if (file-name-absolute-p name) (progn #1#)) nil t (file-name-directory name))))])
#@37 Duplicate setup of current project.
(defalias 'vhdl-duplicate-project #[nil "\304\305!\306	\307#\310\nBC\"\311 *\207" [vhdl-project-alist vhdl-project project-entry new-name read-from-minibuffer "New project name: " aget t append vhdl-update-mode-menu] 5 (#$ . 405004) nil])
#@46 Automatically load project setup at startup.
(defalias 'vhdl-auto-load-project #[nil "\304\211\211\203+\305\n\306\307\310\311@B\312\313\314 Q\"!!\"	\206#\nGA\211\204\n\n\205F\315\316\n@!\317	\320V?#\210	S\nA\211\204/\304+\207" [vhdl-project-file-name list-length file-list file-name-list nil append file-expand-wildcards vhdl-resolve-env-variable vhdl-replace-string "\\(.*\\) \\(.*\\)" "*" " " user-login-name vhdl-import-project expand-file-name t 0] 10 (#$ . 405291)])
(byte-code "\302>\203	\203\303 \210\202\304\305\306\303#\210\306\207" [vhdl-project-auto-load noninteractive startup vhdl-auto-load-project vhdl-run-when-idle 0.1 nil] 4)
#@45 Regexp to match start of construct to hide.
(defconst vhdl-hs-start-regexp "\\(^\\)\\s-*\\(\\(generic\\|port\\)[ 	\n
\f]*(\\|component\\>\\|\\(\\w\\|\\s_\\)+[ 	\n
\f]*:[ 	\n
\f]*\\(\\(component\\|configuration\\|entity\\)[ 	\n
\f]+\\)?\\(\\w\\|\\s_\\)+\\([ 	\n
\f]*(\\(\\w\\|\\s_\\)+)\\)?[ 	\n
\f]*\\(generic\\|port\\)[ 	\n
\f]+map[ 	\n
\f]*(\\|\\(function\\|procedure\\)\\>\\|\\(\\(\\w\\|\\s_\\)+[ 	\n
\f]*:[ 	\n
\f]*\\)?\\(process\\|block\\)\\>\\|configuration\\>\\)" (#$ . 405963))
#@71 Find end of construct to hide (for hideshow).  Only searches forward.
(defalias 'vhdl-hs-forward-sexp-func #[(count) "`\306\307 \310\211\211\311,!\210\312\313!\203B\313 \314@A\"\211\203B@\315\316	!>\203;	\nB\317	\315\310#\210A\211\204&\320\216\321 \210\322\323!\203Y\324\225b\210\325u\210\326 \202
\322\327!\203g\330\331\310\306#\202
\322\332!\203\223\324\225b\210\325u\210\326 \210`\333 \210\322\334!\203\216\324\225b\210\325u\210\326 \210`b\202
\322\335!\203\312\324\225b\210\333 \210\322\336!\203\251\326 \210\330\337\310\306#\203\266\340 \204\251\341\342!\205
\330\343\310\306#\210\325v\210\344 \202
\322\345!\203\351\324\225b\210\330\346\310\306#\205
\342\224\205
\347-!\210\202\324\322\350!\203\367\330\351\310\306#\202
\322\352!\203
\353v\210\344 \202
b.\207" [pos overlay overlay-intangible-list overlay-all-list current-syntax-table case-fold-search t syntax-table nil set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) beginning-of-line looking-at "^\\s-*\\(generic\\|port\\)[ 	\n
\f]*(" 0 -1 forward-sexp "^\\s-*component\\>" re-search-forward "^\\s-*end\\s-+component\\>" "^\\s-*\\w+\\s-*:[ 	\n
\f]*\\(\\(component\\|configuration\\|entity\\)[ 	\n
\f]+\\)?\\w+\\(\\s-*(\\w+)\\)?[ 	\n
\f]*\\(generic\\|port\\)\\s-+map[ 	\n
\f]*(" vhdl-forward-syntactic-ws "port\\s-+map[ 	\n
\f]*(" "^\\s-*\\(function\\|procedure\\)\\s-+\\(\\w+\\|\".+\"\\)" "(" "\\(;\\)\\|\\(\\<is\\>\\)" vhdl-in-literal match-string 2 "^\\s-*\\<begin\\>" vhdl-forward-sexp "^\\s-*\\w+\\s-*:\\s-*block\\>" "^\\s-*\\(\\(\\w+\\s-*:\\s-*block\\>\\)\\|\\(end\\s-+block\\>\\)\\)" vhdl-hs-forward-sexp-func "^\\s-*\\(\\w+\\s-*:\\s-*\\)?process\\>" "^\\s-*end\\s-+process\\>" "^\\s-*configuration\\>" 4 vhdl-mode-ext-syntax-table count] 6 (#$ . 406454)])
#@24 Initialize `hideshow'.
(defalias 'vhdl-hideshow-init #[nil "\205\301\302!\207" [vhdl-hideshow-menu vhdl-hs-minor-mode 1] 2 (#$ . 408472)])
#@49 Toggle hideshow minor mode and update menu bar.
(defalias 'vhdl-hs-minor-mode #[(&optional arg) "\304\305!\210\306\307!\204\310\311!\207\312\313\"\204 \313	\314\315\316\314\257B\n\203.\317\320\321\314\322$\210\2024\323\320\321\322#\210\324!\210\325 \207" [hs-special-modes-alist vhdl-hs-start-regexp vhdl-hide-all-init arg require hideshow boundp hs-block-start-mdata-select vhdl-warning-when-idle "Install included `hideshow.el' patch first (see INSTALL file)" assoc vhdl-mode nil "--\\( \\|$\\)" vhdl-hs-forward-sexp-func add-hook hs-minor-mode-hook hs-hide-all t remove-hook hs-minor-mode force-mode-line-update] 6 (#$ . 408620) "P"])
#@56 Return point if within translate-off region, else nil.
(defalias 'vhdl-within-translate-off #[nil "\212\300\301\302\303#)\205\304\305!\306\232\205`\207" [re-search-backward "^\\s-*--\\s-*pragma\\s-*translate_\\(on\\|off\\)\\s-*\n" nil t match-string 1 "off"] 4 (#$ . 409274)])
#@69 Return point before translate-off pragma if before LIMIT, else nil.
(defalias 'vhdl-start-translate-off #[(limit) "\301\302\303#\205\n\304\224\207" [limit re-search-forward "^\\s-*--\\s-*pragma\\s-*translate_off\\s-*\n" t 0] 4 (#$ . 409561)])
#@67 Return point after translate-on pragma if before LIMIT, else nil.
(defalias 'vhdl-end-translate-off #[(limit) "\301\302\303#\207" [limit re-search-forward "^\\s-*--\\s-*pragma\\s-*translate_on\\s-*\n" t] 4 (#$ . 409812)])
#@76 Match a translate-off block, setting match-data and returning t, else nil.
(defalias 'vhdl-match-translate-off #[(limit) "`W\205'\304 \206\305!\306\211\205&\307!\206\310\nD!\210b)*\207" [limit case-fold-search start end vhdl-within-translate-off vhdl-start-translate-off t vhdl-end-translate-off set-match-data] 4 (#$ . 410041)])
#@132 Match, and move over, any declaration item after point.  Adapted from
`font-lock-match-c-style-declaration-item-and-skip-to-next'.
(defalias 'vhdl-font-lock-match-item #[(limit) "\300\301\302\217\207" [nil (byte-code "\214e}\210\302\303!\205%\304 \305\216\306\225b\210\302\307!\203 \306\225b\202$\310\210\311*)\207" [limit save-match-data-internal looking-at "\\s-*\\([a-zA-Z]\\w*\\)" match-data ((byte-code "\301\302\"\207" [save-match-data-internal set-match-data evaporate] 3)) 1 "\\(\\s-*,\\)" nil t] 2) ((error t))] 3 (#$ . 410393)])
#@68 Mark single quotes as having string quote syntax in 'c' instances.
(defconst vhdl-font-lock-syntactic-keywords '(("\\('\\).\\('\\)" (1 (7 . 39)) (2 (7 . 39)))) (#$ . 410945))
#@48 Regular expressions to highlight in VHDL Mode.
(defvar vhdl-font-lock-keywords nil (#$ . 411126))
(defvar vhdl-font-lock-keywords-0 "For consideration as a value of `vhdl-font-lock-keywords'.\nThis does highlighting of template prompts and directives (pragmas).")
#@121 For consideration as a value of `vhdl-font-lock-keywords'.
This does highlighting of keywords and standard identifiers.
(defvar vhdl-font-lock-keywords-1 nil (#$ . 411397))
#@122 For consideration as a value of `vhdl-font-lock-keywords'.
This does context sensitive highlighting of names and labels.
(defconst vhdl-font-lock-keywords-2 (byte-code "\300\301\302E\303\304\302E\305\306\307\310\311!\205\312\313\314\260\315\302E\316\317\320E\321\322\323\324\325\257\326\327\330\331\310\311!\205/\312\332\333\260\301\302E\334\335\302E\336\315\302E\337\340\341E\342\343D\344\345\346\347F\350\315\351E\352\301\353E\354\355D\356\357D\360\361D\257\207" ["^\\s-*\\(architecture\\|configuration\\|entity\\|package\\(\\s-+body\\)?\\|\\(\\(impure\\|pure\\)\\s-+\\)?function\\|procedure\\|component\\)\\s-+\\(\\w+\\)" 5 font-lock-function-name-face "^\\s-*\\(architecture\\|configuration\\)\\s-+\\w+\\s-+of\\s-+\\(\\w+\\)" 2 "^\\s-*\\(\\w+\\)\\s-*:[ 	\n
\f]*\\(\\(" "assert\\|block\\|case\\|exit\\|for\\|if\\|loop\\|next\\|null\\|" "postponed\\|process\\|" vhdl-standard-p ams "procedural\\|" "with\\|while" "\\)\\>\\|\\w+\\s-*\\(([^\n]*)\\|\\.\\w+\\)*\\s-*<=\\)" 1 "^\\s-*\\(\\w+\\)\\s-*:[ 	\n
\f]*\\(\\w+\\)[ 	\n
\f]*\\(--[^\n]*[ 	\n
\f]+\\)*\\(generic\\|port\\)\\s-+map\\>" (1 font-lock-function-name-face) (2 font-lock-function-name-face) "^\\s-*\\(\\w+\\)\\s-*:[ 	\n
\f]*\\(component\\|configuration\\|entity\\)\\s-+\\(\\w+\\)\\(\\.\\(\\w+\\)\\)?\\(\\s-*(\\(\\w+\\))\\)?" (1 font-lock-function-name-face) (3 font-lock-function-name-face) (5 font-lock-function-name-face nil t) (7 font-lock-function-name-face nil t) "^\\s-*end\\s-+\\(\\(" "architecture\\|block\\|case\\|component\\|configuration\\|entity\\|" "for\\|function\\|generate\\|if\\|loop\\|package\\(\\s-+body\\)?\\|" "procedure\\|\\(postponed\\s-+\\)?process\\|" "units" "\\)\\s-+\\)?\\(\\w*\\)" "^\\s-*\\(\\w+\\s-*:\\s-*\\)?\\(exit\\|next\\)\\s-+\\(\\w*\\)" 3 "^\\s-*attribute\\s-+\\w+\\s-+of\\s-+\\(\\w+\\(,\\s-*\\w+\\)*\\)\\s-*:" "^\\s-*for\\s-+\\(\\w+\\(,\\s-*\\w+\\)*\\)\\>\\s-*\\(:[ 	\n
\f]*\\(\\w+\\)\\|[^i 	]\\)" (1 font-lock-function-name-face) (4 font-lock-function-name-face nil t) "^\\s-*library\\>" (vhdl-font-lock-match-item nil nil (1 font-lock-function-name-face)) "\\<use\\s-+\\(\\(entity\\|configuration\\)\\s-+\\)?\\(\\w+\\)\\(\\.\\(\\w+\\)\\)?\\((\\(\\w+\\))\\)?" (3 font-lock-function-name-face) (5 font-lock-function-name-face nil t) (7 font-lock-function-name-face nil t) "^\\s-*attribute\\s-+\\(\\w+\\)" vhdl-font-lock-attribute-face "^\\s-*\\(\\(sub\\)?\\(nature\\|type\\)\\|end\\s-+\\(record\\|protected\\)\\)\\s-+\\(\\w+\\)" font-lock-type-face "\\(:[^=]\\)" (vhdl-font-lock-match-item (progn (goto-char (match-beginning 1)) (skip-syntax-backward " ") (skip-syntax-backward "w_") (skip-syntax-backward " ") (while (= (preceding-char) 44) (backward-char 1) (skip-syntax-backward " ") (skip-syntax-backward "w_") (skip-syntax-backward " "))) (goto-char (match-end 1)) (1 font-lock-variable-name-face)) "\\(=>\\)" (vhdl-font-lock-match-item (progn (goto-char (match-beginning 1)) (skip-syntax-backward " ") (while (= (preceding-char) 41) (backward-sexp)) (skip-syntax-backward "w_") (skip-syntax-backward " ") (when (memq (preceding-char) '(110 78 124)) (goto-char (point-max)))) (goto-char (match-end 1)) (1 font-lock-variable-name-face)) "\\<\\(alias\\|for\\|group\\|quantity\\)\\s-+\\w+\\s-+\\(across\\|in\\|is\\)\\>" (vhdl-font-lock-match-item (progn (goto-char (match-end 1)) (match-beginning 2)) nil (1 font-lock-variable-name-face))] 17) (#$ . 411577))
#@113 For consideration as a value of `vhdl-font-lock-keywords'.
This does highlighting of words with special syntax.
(defvar vhdl-font-lock-keywords-3 nil (#$ . 414948))
#@113 For consideration as a value of `vhdl-font-lock-keywords'.
This does highlighting of additional reserved words.
(defvar vhdl-font-lock-keywords-4 nil (#$ . 415120))
#@120 For consideration as a value of `vhdl-font-lock-keywords'.
This does background highlighting of translate-off regions.
(defconst vhdl-font-lock-keywords-5 '((vhdl-match-translate-off (0 vhdl-font-lock-translate-off-face append))) (#$ . 415292))
#@31 Face name to use for prompts.
(defvar vhdl-font-lock-prompt-face 'vhdl-font-lock-prompt-face (#$ . 415543))
#@47 Face name to use for standardized attributes.
(defvar vhdl-font-lock-attribute-face 'vhdl-font-lock-attribute-face (#$ . 415657))
#@55 Face name to use for standardized enumeration values.
(defvar vhdl-font-lock-enumvalue-face 'vhdl-font-lock-enumvalue-face (#$ . 415793))
#@59 Face name to use for standardized functions and packages.
(defvar vhdl-font-lock-function-face 'vhdl-font-lock-function-face (#$ . 415937))
#@34 Face name to use for directives.
(defvar vhdl-font-lock-directive-face 'vhdl-font-lock-directive-face (#$ . 416083))
#@49 Face name to use for additional reserved words.
(defvar vhdl-font-lock-reserved-words-face 'vhdl-font-lock-reserved-words-face (#$ . 416206))
#@45 Face name to use for translate-off regions.
(defvar vhdl-font-lock-translate-off-face 'vhdl-font-lock-translate-off-face (#$ . 416354))
(byte-code "\304\211\203&\305\306\n@@\307#\310\311	\312	D\313\n@@\314QF!\210\nA\211\204*\315\316\304\317\320\321%\210\322\316\323\324#\210\322\316\325\324#\210\322\316\326\324#\210\322\316\327\324#\210\322\316\330\324#\210\322\316\331\324#\210\332\333\334\335\320\316%\210\332\336\337\340\320\316%\210\332\341\342\343\320\316%\210\332\344\345\346\320\316%\210\332\347\350\351\320\316%\210\332\352\353\354\320\316%\210\332\355\356\357\320\316%\210\211\203\306\310\360\305\306\n\211@@)\307#\312\361\362\363\n@8DD\364\362\365\n@8DD\366BBD\367\n@@\314Q\370BBBB!\210\nA\211\204\221)\304\207" [vhdl-special-syntax-alist name syntax-alist x nil vhdl-function-name "vhdl-font-lock" "face" eval defvar quote "Face name to use for " "." custom-declare-group vhdl-highlight-faces "Faces for highlighting." :group vhdl-highlight custom-add-to-group font-lock-comment-face custom-face font-lock-string-face font-lock-keyword-face font-lock-type-face font-lock-function-name-face font-lock-variable-name-face custom-declare-face vhdl-font-lock-prompt-face ((((min-colors 88) (class color) (background light)) (:foreground "Red1" :bold t)) (((class color) (background light)) (:foreground "Red" :bold t)) (((class color) (background dark)) (:foreground "Pink" :bold t)) (t (:inverse-video t))) "Font lock mode face used to highlight prompts." vhdl-font-lock-attribute-face ((((class color) (background light)) (:foreground "Orchid")) (((class color) (background dark)) (:foreground "LightSteelBlue")) (t (:italic t :bold t))) "Font lock mode face used to highlight standardized attributes." vhdl-font-lock-enumvalue-face ((((class color) (background light)) (:foreground "SaddleBrown")) (((class color) (background dark)) (:foreground "BurlyWood")) (t (:italic t :bold t))) "Font lock mode face used to highlight standardized enumeration values." vhdl-font-lock-function-face ((((class color) (background light)) (:foreground "Cyan4")) (((class color) (background dark)) (:foreground "Orchid1")) (t (:italic t :bold t))) "Font lock mode face used to highlight standardized functions and packages." vhdl-font-lock-directive-face ((((class color) (background light)) (:foreground "CadetBlue")) (((class color) (background dark)) (:foreground "Aquamarine")) (t (:italic t :bold t))) "Font lock mode face used to highlight directives." vhdl-font-lock-reserved-words-face ((((class color) (background light)) (:foreground "Orange" :bold t)) (((min-colors 88) (class color) (background dark)) (:foreground "Yellow1" :bold t)) (((class color) (background dark)) (:foreground "Yellow" :bold t)) (t nil)) "Font lock mode face used to highlight additional reserved words." vhdl-font-lock-translate-off-face ((((class color) (background light)) (:background "LightGray")) (((class color) (background dark)) (:background "DimGray")) (t nil)) "Font lock mode face used to background highlight translate-off regions." defface ((class color) (background light)) :foreground 2 ((class color) (background dark)) 3 ((t nil)) "Font lock mode face used to highlight " (:group 'vhdl-highlight-faces)] 10)
#@27 Initialize fontification.
(defalias 'vhdl-font-lock-init #[nil "\306\307Q\310\311\312F\313	\314Q\310\315\312F\316\317\320EE\321P\322\323E\f\322\324E
\322\325E\"\322\325E#\322\326E$\322\327E%\322\330E\257&'\331(\211)\203l\332)@A@\333Q\322\334\335)@@\336#\337)@8F(B()A\211)\204G(**+\322\340EC,\341\n-\205\202&.\204\214/\205\216,0\205\225*1\205\23423\205\2434&\2115\207" [vhdl-template-prompt-syntax vhdl-directive-keywords-regexp vhdl-font-lock-keywords-0 vhdl-attributes-regexp vhdl-types-regexp vhdl-functions-regexp "\\(^\\|[ 	(.']\\)\\(<" ">\\)" 2 vhdl-font-lock-prompt-face t "--\\s-*" "\\s-+\\(.*\\)$" vhdl-font-lock-directive-face "^#[ 	]*\\(\\w+\\)\\([ 	]+\\(\\w+\\)\\)?" (1 font-lock-builtin-face) (3 font-lock-variable-name-face nil t) "'" 1 vhdl-font-lock-attribute-face font-lock-type-face vhdl-font-lock-function-face vhdl-font-lock-enumvalue-face font-lock-constant-face font-lock-keyword-face nil "\\(" "\\)" vhdl-function-name "vhdl-font-lock" "face" 4 vhdl-font-lock-reserved-words-face append vhdl-packages-regexp vhdl-enum-values-regexp vhdl-constants-regexp vhdl-keywords-regexp vhdl-font-lock-keywords-1 vhdl-special-syntax-alist keywords syntax-alist vhdl-font-lock-keywords-3 vhdl-reserved-words-regexp vhdl-font-lock-keywords-4 vhdl-highlight-keywords vhdl-highlight-forbidden-words vhdl-highlight-verilog-keywords vhdl-highlight-special-words vhdl-highlight-names vhdl-font-lock-keywords-2 vhdl-highlight-translate-off vhdl-font-lock-keywords-5 vhdl-font-lock-keywords] 10 (#$ . 419579)])
(vhdl-font-lock-init)
#@49 Re-initialize fontification and fontify buffer.
(defalias 'vhdl-fontify-buffer #[nil "\302\303?\304BBB\305\306!\203\306 \210\307 \210\310\303!\210\310\311!\207" [vhdl-highlight-case-sensitive font-lock-defaults vhdl-font-lock-keywords nil (((95 . "w")) beginning-of-line) fboundp font-lock-unset-defaults font-lock-set-defaults font-lock-mode t] 4 (#$ . 421163) nil])
#@67 Initialize custom face and page settings for PostScript printing.
(defalias 'vhdl-ps-print-settings #[nil "\203	\204\306\302!\210\307\306\303!\210\310\306\304!\210\311\312\205h\306\313!\210\312\306\314!\210\315\f\306\316!\210\317\306\320!\210\321\306\322!\210\323\306\324!\210\325\326=\205h\306\327!\210\330\306\331!\210\332\306\333!\210\334\211\207" [vhdl-print-customize-faces ps-print-color-p ps-bold-faces ps-italic-faces ps-underlined-faces ps-always-build-face-reference make-local-variable (font-lock-keyword-face font-lock-type-face vhdl-font-lock-attribute-face vhdl-font-lock-enumvalue-face vhdl-font-lock-directive-face) (font-lock-comment-face font-lock-function-name-face font-lock-type-face vhdl-font-lock-attribute-face vhdl-font-lock-enumvalue-face vhdl-font-lock-directive-face) (font-lock-string-face) t ps-landscape-mode ps-number-of-columns 2 ps-font-size 7.0 ps-header-title-font-size 10.0 ps-header-font-size 9.0 ps-header-offset 12.0 letter ps-inter-column 40.0 ps-left-margin 40.0 ps-right-margin 40.0 vhdl-print-two-column ps-paper-type] 2 (#$ . 421541)])
#@33 Initialize PostScript printing.
(defalias 'vhdl-ps-print-init #[nil "\300\301\302\303\304$\207" [add-hook ps-print-hook vhdl-ps-print-settings nil t] 5 (#$ . 422660)])
#@81 Cache with entities and corresponding architectures for each
project/directory.
(defvar vhdl-entity-alist nil (#$ . 422834))
#@55 Cache with configurations for each project/directory.
(defvar vhdl-config-alist nil (#$ . 422965))
#@49 Cache with packages for each project/directory.
(defvar vhdl-package-alist nil (#$ . 423070))
#@62 Cache with instantiated entities for each project/directory.
(defvar vhdl-ent-inst-alist nil (#$ . 423170))
#@66 Cache with design units in each file for each project/directory.
(defvar vhdl-file-alist nil (#$ . 423284))
#@49 Cache with source directories for each project.
(defvar vhdl-directory-alist nil (#$ . 423398))
#@99 Alist of design units simultaneously open in the current speedbar for each
directory and project.
(defvar vhdl-speedbar-shown-unit-alist nil (#$ . 423500))
#@63 List of projects simultaneously open in the current speedbar.
(defvar vhdl-speedbar-shown-project-list nil (#$ . 423662))
#@54 List of projects and directories with updated files.
(defvar vhdl-updated-project-list nil (#$ . 423790))
#@64 List of modified files to be rescanned for hierarchy updating.
(defvar vhdl-modified-file-list nil (#$ . 423902))
#@46 Depth of instantiation hierarchy to display.
(defvar vhdl-speedbar-hierarchy-depth 0 (#$ . 424022))
#@90 Non-nil means project hierarchy is displayed in speedbar, directory
hierarchy otherwise.
(defvar vhdl-speedbar-show-projects nil (#$ . 424128))
#@41 Return position of end of current unit.
(defalias 'vhdl-get-end-of-unit #[nil "`\212\301\302\303\304#\203 \212\305\224b\210\306 \210h\307U?\205o?)\204\310\311\304#\210`*\207" [pos re-search-forward "^[ 	]*\\(architecture\\|configuration\\|entity\\|package\\)\\>" nil 1 0 vhdl-backward-syntactic-ws 59 re-search-backward "^[ 	]*end\\>"] 4 (#$ . 424278)])
#@53 Like `match-string-no-properties' with down-casing.
(defalias 'vhdl-match-string-downcase #[(num &optional string) "\303	\"\211\205\n\227)\207" [num string match match-string-no-properties] 4 (#$ . 424645)])
#@54 Scan the context clause that precedes a design unit.
(defalias 'vhdl-scan-context-clause #[nil "\301\212\302\303\301\304#\203/\302\305\301\304#\203/\306\307!\226\310\232\203/\311\312!\203\313\307!\314\315!BB\202))\207" [lib-alist nil re-search-backward "^[ 	]*\\(architecture\\|configuration\\|entity\\|package\\)\\>" t "^[ 	]*\\(end\\|use\\)\\>" match-string 1 "USE" looking-at "^[ 	]*use[ 	\n
\f]*\\(\\w+\\)\\.\\(\\w+\\)\\.\\w+" match-string-no-properties vhdl-match-string-downcase 2] 4 (#$ . 424863)])
#@64 Scan contents of VHDL files in directory or file pattern NAME.
(defalias 'vhdl-scan-directory-contents #[(name &optional project update num-string non-final) "\306\307\"\210\310\311\"\310\312\"\211G\313U\f\203C\202/\203(\314\315	\"\202/\316	\315\317\n!#@\2066	A\320\321B@\"8\206D\322CD@EDA@@FDA@A@G\323\2110H\323\211IJ\323\211KL\323\211MN\323\211OP@\204\201\f\203\257\321QA\315#0\321RA\315#H\321SA\315#I\321TA\315#@J\321UA\315#K\204\274
\204\274\324\325\"\210
O
\203\354
GN\324\326\203\321\327\202\322\330V\206\330\322$\210C\322\232\204
\323\211WX
\203
\306C
@\"\204\374
@WBW
A\211\204\354W\237*
\203\354Y\2041
\324\331\203
\327\202
\330V\206\"
\322N
GZ\332_N\245\333&\210\334
@!\323\211\211\211\211\211\211\211Z[\\]^_`a\211b\204\233\315\335 \323\211\211cdefX\336g!\210\337\340!\203\245
\340 e\341e@eA\"\211e\203\245
e@c\342\343c!>\203\234
cdBd\344c\342\323#\210eA\211e\204\200
\345\216\212E\203\301
E\346 W\203\301
\324\347b\"\210\315P\202eb\210\350\351\323\315#\203\"\352\311!\211h\227i\3210i\315#j\353 kjA@\203\377
\354\355hjA@\312j8b\356 &\210\202iaBa\357\360ihb\356 \320j8\361j8k\257#\210,\202\304
eb\210\350\362\323\315#\203\276\352\311!\211l\227m\352\312!\211h\227i\3210i\315#j\320j84\3214m\315#n\353 on\203x\354\363lhnA@\312n8b\356 &\210\202\271m`B`i_B_\357\364mlb\356 \323o\257#\210\357\360ij@\206\243hjA@\312j8\3654!m\366j8\257#\210.\202%eb\210\350\367\323\315#\203\307\352\311!\211p\227q\321Hq\315#r\352\312!\211h\227i\353 k\356 s\370 t\323\211mu\323\211vw\323\211xy\323\211z{\371\372!\203\373\311!mr\2030\354\374phrA@\312r8bs&\210\202\302q^B^\350\375t\315#\203\252\373\320!w\376\373\311!\377\"v\201\223 \210\201\224\201\225!\2037\373\320!{\310\312!\205j\373\361!x\310\312!\205w\373\201\226!y\310\312!?\205\203\373\361!zv\2037v@wxyz{\257uBuvA\211v\204\212\2027\357\201Hqpbsimuk\257#\210.\202\301eb\210\350\201\227\323\315#\203\352\312!\211|\227}\352\311!~\321I}\315#\356 \200\370 t\323\211\201\202\323\211\203\204\323k~\203\201\2268\202A@\203W\354\201\230~\203&\201\231\202'\322|~\2037\201\2268\202;A@~\203I\201\2328\202M\3128b\356 &\210\202\353 k\350\201\233t\315#\203\235\310\311!\226\201\234\232\203\207\352\312!\211\201\227\201b\356 F\203B\203\202[\352\312!\211\202\227\202b\356 F\204B\204\202[\204\237\204\203\237\203~\203\266}\\B\\\202\275}]B]\357\201I}~\203\361@\206\320|A@\3128\3208\3618\3668b\200\204k\257\n\202|b\200\203\204k\201\2268\201\2328\201\2358\201\2368\257\n#\210.\202\312F\2039F\346 W\2039\324\201\237b\"\210\315P\202teb\210\350\362\323\315#\203t\352\312!\211h\227i\352\311!\211l\227m\3210i\315#j\320j84\3214m\315#n`\205\370 t\313\206\323\211\207\210\350\201\240t\315#\203CG\203\232\206T\211\206GX\203C\310\201\241!\203\255\352\311!\210B\210\202~\310\201\242!\203\275\210A\210\202~\352\311!\211\211\227\212\352\320!\206\321\352\201\226!\213\310\201\235!\203\343\373\201\243!\206\353\213\205\353\213\227x\373\201\244!y\310\201\235!?\205\373\201\243!z\373\201\245!{\311\225b\210\212[B[xZBZ\341\207\212\211b\356 \213xyz{\201\246\210!\257\nC\"\207.\202~\205b\210\350\201\247t\315#\203\352\320!\213\310\201\226!\205d\373\201\236!x\373\201\243!y\310\201\226!?\205{\373\201\236!z\373\201\235!{\376\373\311!\377\"v\207\214\323\215\214\203v@\201\250\232\204\254\214@@v\235\203
\361\214@8\206\265\322\227\213\227\232\203
\214@\215x\206\313\366\2158\201\251\366\2158Z\"BZ\215@\215A@\312\2158\320\2158\361\2158x\206\364\366\2158y\206\377\201\226\2158z{\257	\215\214\215\240\210\214A\211\214\204\230.\202G\357\364mn@nA@\312n8\207\361n8\257#\210\357\360ij@jA@\312j8\3654!\361j8\366j8\257#\210G\203k\206GV\203k\324\201\252b\"\210\315Ptb\210.\f\202<\357\201Kba`_^]\\[Z\257#\210\341ZJ\"J.\202\343\201\253b!\204\343p\201\254b!\323\216\217\220\217\203\275\217q\204\310\323\201\255\201\256\217\203\323\201\257\201\260\201\261\217\210\216\203\336\201\262p!\210\220q\210+.	
A\211\204\f
@\204\366O\204@\203\372\221\204\3720\211L\2038\312L@8\204/\361L@8@M\354\201\263MA@L@A@\312M8\320M8%\210LA\211L\204H\211L\203\246\3210\361L@8\315#\211M\203\202\321\320M8\366L@8\315#\204\235L@M\354\201\264MA@\361M8\366M8\312M8\320M8&\210\202\235L@M\354\201\265MA@\361M8\312M8\320M8%\210LA\211L\204@I\211L\203\332\312L@8\204\321L@M\354\201\266MA@\201\232M8\201\235M8$\210LA\211L\204\256\3650!0\365H!H\365I!I\201\267\201\270@\206\370	\"\210@\2041	\201\271\201QA\"\210\201\271\201RA\"\210\201\271\201SA\"\210\201\271\201TA\"\210\201\271\201UA\"\210\357\201QA0#\210\357\201RAH#\210\357\201SAI#\210\357\201TAJC#\210\357\201UAK#\210\324\201\272\203p	\327\202q	\330V\206w	\322$\210@\204\205	\324\201\273!\210P\203\220	\354\201\274!\210@\203\232	\221\204\253	Y\203\253	\222\203\253	\201\275A!\210.\315\207" [name dir-name file-pattern is-directory update file-list string-match "\\(.*[/\\]\\)\\(.*\\)" match-string 1 2 0 vhdl-get-source-files t vhdl-directory-files wildcard-to-regexp 3 aget #15="" nil message "No such file: \"%s\"" "Scanning %s %s\"%s\"..." "directory" "files" "Scanning %s %s\"%s\"... (%2d%s)" 100 "%" abbreviate-file-name syntax-table set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) buffer-size #1="WARNING:  Scan limit (design units: file size) reached in file:\n  \"%s\"" re-search-forward #2="^[ 	]*entity[ 	\n
\f]+\\(\\w+\\)[ 	\n
\f]+is\\>" match-string-no-properties vhdl-scan-context-clause vhdl-warning-when-idle #3="Entity declared twice (used 1.): \"%s\"\n  1. in \"%s\" (line %d)\n  2. in \"%s\" (line %d)" vhdl-current-line aput ent-alist 4 #4="^[ 	]*architecture[ 	\n
\f]+\\(\\w+\\)[ 	\n
\f]+of[ 	\n
\f]+\\(\\w+\\)[ 	\n
\f]+is\\>" #5="Architecture declared twice (used 1.): \"%s\" of \"%s\"\n  1. in \"%s\" (line %d)\n  2. in \"%s\" (line %d)" arch-alist vhdl-sort-alist 5 #6="^[ 	]*configuration[ 	\n
\f]+\\(\\w+\\)[ 	\n
\f]+of[ 	\n
\f]+\\(\\w+\\)[ 	\n
\f]+is\\>" vhdl-get-end-of-unit vhdl-re-search-forward #7="\\<for[ 	\n
\f]+\\(\\w+\\)" vhdl-match-string-downcase #8="Configuration declared twice (used 1.): \"%s\" of \"%s\"\n  1. in \"%s\" (line %d)\n  2. in \"%s\" (line %d)" #9="^[ 	]*for[ 	\n
\f]+\\(\\w+\\([ 	\n
\f]*,[ 	\n
\f]*\\w+\\)*\\)[ 	\n
\f]*:[ 	\n
\f]*\\(\\w+\\)[ 	\n
\f]+" split-string #10="[ 	\n
\f]*,[ 	\n
\f]*" project key vhdl-project-alist file-exclude-regexp vhdl-speedbar-scan-limit limit-design-file-size limit-hier-file-size limit-hier-inst-no conf-alist pack-alist ent-inst-list file-alist tmp-list tmp-entry no-files files-exist big-files vhdl-entity-alist vhdl-config-alist vhdl-package-alist vhdl-ent-inst-alist vhdl-file-alist num-string file-tmp-list case-fold-search noninteractive inst-ent-list inst-list pack-body-list pack-list conf-list arch-ent-list arch-list ent-list file-name overlay overlay-intangible-list overlay-all-list current-syntax-table vhdl-mode-ext-syntax-table ent-name ent-key ent-entry lib-alist arch-name arch-key arch-entry lib-arch-alist conf-name conf-key conf-entry conf-line end-of-unit comp-conf-list inst-key-list inst-comp-key inst-ent-key inst-arch-key inst-conf-key inst-lib-key pack-name pack-key is-body pack-entry pack-line comp-name func-name comp-alist func-alist beg-of-unit inst-no inst-alist inst-path inst-name inst-key inst-comp-name tmp-inst-alist inst-entry file-opened visiting-buffer source-buffer non-final vhdl-speedbar-save-cache vhdl-forward-syntactic-ws looking-at #11="use[ 	\n
\f]+\\(\\(entity\\)\\|configuration\\)[ 	\n
\f]+\\(\\w+\\)\\.\\(\\w+\\)[ 	\n
\f]*\\((\\(\\w+\\))\\)?" 6 #12="^[ 	]*package[ 	\n
\f]+\\(body[ 	\n
\f]+\\)?\\(\\w+\\)[ 	\n
\f]+is\\>" #13="Package%s declared twice (used 1.): \"%s\"\n  1. in \"%s\" (line %d)\n  2. in \"%s\" (line %d)" #14=" body" 7 #16="^[ 	]*\\(component\\|function\\|procedure\\)[ 	\n
\f]+\\(\\w+\\|\".*\"\\)" #17="COMPONENT" 8 9 #18="WARNING:  Scan limit (hierarchy: file size) reached in file:\n  \"%s\"" "^[ 	]*\\(\\w+\\)[ 	\n
\f]*:[ 	\n
\f]*\\(\\(\\w+\\)[ 	\n
\f]+\\(--[^\n]*\n[ 	\n
\f]*\\)*\\(generic\\|port\\)[ 	\n
\f]+map\\>\\|component[ 	\n
\f]+\\(\\w+\\)\\|\\(\\(entity\\)\\|configuration\\)[ 	\n
\f]+\\(\\(\\w+\\)\\.\\)?\\(\\w+\\)\\([ 	\n
\f]*(\\(\\w+\\))\\)?\\|\\(\\(for\\|if\\)\\>[^;:]+\\<generate\\>\\|block\\>\\)\\)\\|\\(^[ 	]*end[ 	\n
\f]+\\(generate\\|block\\)\\>\\)" 14 16 11 13 10 reverse "^[ 	]*for[ 	\n
\f]+\\(\\w+\\([ 	\n
\f]*,[ 	\n
\f]*\\w+\\)*\\)[ 	\n
\f]*:[ 	\n
\f]*\\(\\w+\\)[ 	\n
\f]+\\(--[^\n]*\n[ 	\n
\f]*\\)*use[ 	\n
\f]+\\(\\(entity\\)\\|configuration\\)[ 	\n
\f]+\\(\\(\\w+\\)\\.\\)?\\(\\w+\\)\\([ 	\n
\f]*(\\(\\w+\\))\\)?" #19="all" vhdl-delete #20="WARNING:  Scan limit (hierarchy: instances per architecture) reached in file:\n  \"%s\"" file-directory-p find-buffer-visiting (byte-code "\302!q\210\303\304!\210\305\306\307\310 #\210\305\311\312\310 #\210\305\313\312\310 #\210\305\314\315\310 #\210\303\207" [file-name file-opened create-file-buffer t vhdl-insert-file-contents modify-syntax-entry 45 ". 12" syntax-table 10 ">" 13 95 "w"] 4) ((error (byte-code "\301\302\303\"\304\"\210\305\207" [file-name vhdl-warning format "File cannot be opened: \"%s\"" t nil] 4))) info (byte-code "\306\307 \310\211\211\311
!\210\312\313!\203?\313 \314\n@\nA\"\211\203?\n@\315\316!>\2038	B\317\315\310#\210\nA\211\204#\320\216\212@\203[@\321 W\203[\322\323A\"\210\306B\202\224eb\210\324\325\310\306#\203\274\326\327!\211C\227D\330D\306#E\331 FEA@\203\231\332\333CEA@\334E8A\335 &\210\202\270DGBG\336\337DCA\335 \340E8\341E8F\257#\210,\202^eb\210\324\342\310\306#\203X
\326\327!\211H\227I\326\334!\211C\227D\330D\306#E\340E8$\330$I\306#J\331 KJ\203
\332\343HCJA@\334J8A\335 &\210\202S
ILBLDMBM\336\344IHA\335 \310K\257#\210\336\337DE@\206=
CEA@\334E8\345$!I\346E8\257#\210.\202\277eb\210\324\347\310\306#\203W\326\327!\211N\227O\3305O\306#P\326\334!\211C\227D\331 F\335 Q\350 R\310\211IS\310\211TU\310\211VW\310\211XY\351\352!\203\255
\353\327!IP\203\312
\332\354NCPA@\334P8AQ&\210\202ROZBZ\324\355R\306#\203<\353\340!U\356\353\327!\357\"T\360 \210\361\362!\203\321
\353\340!Y\363\334!\205\376
\353\341!V\363\334!\205	\353\364!W\363\334!?\205\353\341!XT\203\321
T@UVWXY\257SBSTA\211T\204\202\321
\336\365ONAQDISF\257#\210.\202[
eb\210\324\366\310\306#\203\224\326\334!\211[\227\\\326\327!]\330=\\\306#^\335 _\350 R\310\211`a\310\211bc\310F]\203\234\364^8\202\240^A@\203\333\332\367]\203\256\370\202\257\371[]\203\275\364^8\202\301^A@]\203\315\372^8\202\321\334^8A\335 &\210\202\217\331 F\324\373R\306#\203\363\327!\226\374\232\203\326\334!\211`\227`A\335 FbBb\202\337\326\334!\211a\227aA\335 FcBc\202\337c\237cb\237b]\2036\\dBd\202=\\eBe\336\375\\]\203o^@\206N[^A@\334^8\340^8\341^8\346^8A_cF\257\n\202\215[A_bcF\364^8\372^8\376^8\377^8\257\n#\210.\202Zf\203\257f\321 W\203\257\322\201tA\"\210\306B\202\332eb\210\324\342\310\306#\203\332\326\334!\211C\227D\326\327!\211H\227I\330D\306#E\340E8$\330$I\306#J`g\350 R\201uh\310\211ij\324\201vR\306#\203\265k\203hT\211hkX\203\265\363\201w!\203%\326\327!jBj\202\366\363\201x!\2035jAj\202\366\326\327!\211l\227m\326\340!\206G\326\364!n\363\376!\203W\353\201y!\206_n\205_n\227V\353\201z!W\363\376!?\205t\353\201y!X\353\201{!Y\327\225b\210moBoVpBp\314imlA\335 nVWXY\201|j!\257\nC\"i.\202\366gb\210\324\201}R\306#\203\201\326\340!n\363\364!\205\322\353\377!V\353\201y!W\363\364!?\205\345\353\377!X\353\376!Y\356\353\327!\357\"Tiq\310rq\203|T@\201~\232\204q@@T\235\203s\341q@8\206\371\227n\227\232\203sq@rV\2063\346r8\201\346r8p\"Bpr@rA@\334r8\340r8\341r8V\206\\\346r8W\206e\364r8XY\257	rqr\240\210qA\211q\204.\202\271\336\344IJ@JA@\334J8i\341J8\257#\210\336\337DE@EA@\334E8\345$!\341E8\346E8\257#\210k\203\321hkV\203\321\322\201\200A\"\210\306BRb\210.\f\202\262\336\201\201AGLMZedop\257#\210\314ps\"s.\310\207" [overlay overlay-intangible-list overlay-all-list current-syntax-table case-fold-search vhdl-mode-ext-syntax-table t syntax-table nil set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) buffer-size message #1# re-search-forward #2# match-string-no-properties 1 aget vhdl-scan-context-clause vhdl-warning-when-idle #3# 2 vhdl-current-line aput ent-alist 3 4 #4# #5# arch-alist vhdl-sort-alist 5 #6# vhdl-get-end-of-unit vhdl-re-search-forward #7# vhdl-match-string-downcase #8# #9# split-string #10# vhdl-forward-syntactic-ws looking-at #11# match-string 6 conf-alist #12# #13# #14# #15# 7 #16# #17# pack-alist 8 9 limit-design-file-size file-name big-files ent-name ent-key ent-entry lib-alist ent-list arch-name arch-key arch-entry lib-arch-alist arch-list arch-ent-list conf-name conf-key conf-entry conf-line end-of-unit comp-conf-list inst-key-list inst-comp-key inst-ent-key inst-arch-key inst-conf-key inst-lib-key conf-list pack-name pack-key is-body pack-entry pack-line comp-name func-name comp-alist func-alist pack-body-list pack-list limit-hier-file-size beg-of-unit inst-no inst-alist inst-path limit-hier-inst-no inst-name inst-key inst-comp-name inst-list inst-ent-list tmp-inst-alist inst-entry ent-inst-list #18# 0 "^[ 	]*\\(\\w+\\)[ 	\n
\f]*:[ 	\n
\f]*\\(\\(\\w+\\)[ 	\n
\f]+\\(--[^\n]*\n[ 	\n
\f]*\\)*\\(generic\\|port\\)[ 	\n
\f]+map\\>\\|component[ 	\n
\f]+\\(\\w+\\)\\|\\(\\(entity\\)\\|configuration\\)[ 	\n
\f]+\\(\\(\\w+\\)\\.\\)?\\(\\w+\\)\\([ 	\n
\f]*(\\(\\w+\\))\\)?\\|\\(\\(for\\|if\\)\\>[^;:]+\\<generate\\>\\|block\\>\\)\\)\\|\\(^[ 	]*end[ 	\n
\f]+\\(generate\\|block\\)\\>\\)" 14 16 11 13 10 reverse "^[ 	]*for[ 	\n
\f]+\\(\\w+\\([ 	\n
\f]*,[ 	\n
\f]*\\w+\\)*\\)[ 	\n
\f]*:[ 	\n
\f]*\\(\\w+\\)[ 	\n
\f]+\\(--[^\n]*\n[ 	\n
\f]*\\)*use[ 	\n
\f]+\\(\\(entity\\)\\|configuration\\)[ 	\n
\f]+\\(\\(\\w+\\)\\.\\)?\\(\\w+\\)\\([ 	\n
\f]*(\\(\\w+\\))\\)?" #19# vhdl-delete #20# file-alist] 15) ((error (byte-code "\302\211A@)!\207" [info x vhdl-warning] 3))) kill-buffer "Architecture of non-existing entity: \"%s\" of \"%s\"\n  in \"%s\" (line %d)" "Configuration of non-existing architecture: \"%s\" of \"%s(%s)\"\n  in \"%s\" (line %d)" "Configuration of non-existing entity: \"%s\" of \"%s\"\n  in \"%s\" (line %d)" "Package body of non-existing package: \"%s\"\n  in \"%s\" (line %d)" add-to-list vhdl-updated-project-list adelete "Scanning %s %s\"%s\"...done" "Scanning directory...done" "Scanning is incomplete.\n  --> see user option `vhdl-speedbar-scan-limit'" vhdl-save-cache] 15 (#$ . 425386)])
#@84 Scan the contents of all VHDL files found in the directories and files
of PROJECT.
(defalias 'vhdl-scan-project-contents #[(project) "\306\307	\"8\206\n\310\311\307	\"A@!\312\307	\"8\206\313\314\211\211\211\211\211*%+,-\315\316	\"\210\315\317	\"\210\315\320	\"\210\315\321	\"\210\315\322	\"\210\323\324!\210-\203\210\311-@!*\325\326*\"\210\327\330*\"\327\312*\"\n\331
!\203v\313\202x,
Q%B%-A\211-\204R\332%!\211%\203\301%@*\325\333*\"\203\257\334-\335\327\330*\"!\"-\202\270\334-*C\"-%A\211%\204\222+\313\232\204\361\314.-\203\353\325+-@\"\204\342-@%B%-A\211-\204\320%\237-)\323\336!\210\314%-G\330-\203+
\337\340-@!!\341
	\314\342\343\f#-A%\210\344\345\346
!\"\210-A-T\202\376\347\350	%\237C#\210\323\351	\".	\207" [vhdl-project-alist project recursive act-dir num-dir dir-name 2 aget (#1="") vhdl-resolve-env-variable 3 #1# nil adelete vhdl-entity-alist vhdl-config-alist vhdl-package-alist vhdl-ent-inst-alist vhdl-file-alist message "Collecting source files..." string-match "\\(\\(-r \\)?\\)\\(.*\\)" match-string 1 file-name-absolute-p vhdl-resolve-paths "-r \\(.*[/\\]\\)" append vhdl-get-subdirs "Collecting source files...done" abbreviate-file-name expand-file-name vhdl-scan-directory-contents format "(%s/%s) " add-to-list dir-list-tmp file-name-directory aput vhdl-directory-alist "Scanning project \"%s\"...done" dir file-exclude-regexp default-dir dir-list case-fold-search] 10 (#$ . 441023)])
#@61 Update hierarchy information by contents of current buffer.
(defalias 'vhdl-update-file-contents #[(file-name) "\306!\307!\n\310\203\226	@A@\235\203\217@@\311 \"\312\"\206*	\313#\312\"\2067	\313#\312\"\206D	\313#\312\"\206Q	\313#@#\312$\"\206_	\313#%\312%\313#\211&@'&A@(\314&8)\315&8*\316&8+\317&8,\320&8-\"\206\231	.\310\211/\310\21101'\203\356'@/\312/\313#11A@\232\203\345\31518\203\337\321\322/1@\310\211\31518\310\257#\210\202\345\323\322/\"\210'A\211'\204\254(\203_
(@/)@0\3120\313#1\31518\312/\313#A@\232\203R
\323\324/\"\2101A@\204,
\203L
\321\32201@1A@\31418\31618\31718\257#\210\202R
\323\3220\"\210(A()A)\202\356*\203\206
*@/\312/\313#A@\232\203}
\323\325/\"\210*A\211*\204d
+\203\333
+@/\312/\313#11A@\232\203\322
\32618\203\314
\321\327/1@\310\211\211\211\211\32618\32018\33018\33118\257\n#\210\202\322
\323\327/\"\210+A\211+\204\213
,\2033,@/\312/\313#1\32618\232\203*1A@\203$\321\327/1@1A@\31418\31518\31618\31718\310\211\211\211\257\n#\210\202*\323\327/\"\210,A\211,\204\340
-\203J\332-@#\"#-A\211-\2048\333\334.#\210\333\335.#\210\333\336.#\210\333\337.#C#\210\340\"\313#\2102\203|\"\204\2062\204\213\"\204\213\341\"!\210\313.A\211\204\f+\207" [file-name dir-name vhdl-directory-alist directory-alist updated vhdl-project abbreviate-file-name file-name-directory nil vhdl-project-p aget t 2 3 4 5 7 aput ent-alist adelete arch-alist conf-alist 6 pack-alist 8 9 vhdl-delete vhdl-aput vhdl-entity-alist vhdl-config-alist vhdl-package-alist vhdl-ent-inst-alist vhdl-scan-directory-contents vhdl-speedbar-refresh project ent-inst-list vhdl-file-alist file-alist file-entry ent-list arch-list arch-ent-list conf-list pack-list pack-body-list inst-ent-list cache-key key ent-key entry vhdl-speedbar-show-projects] 15 (#$ . 442517)])
#@57 Update directory and hierarchy information in speedbar.
(defalias 'vhdl-update-hierarchy #[nil "\304!\305\205.\n\205.\n\203\"\306\n@!\206	\nA\211\204\305\307 \210	\205.\310\311!*\207" [vhdl-modified-file-list updated file-list vhdl-speedbar-update-on-saving reverse nil vhdl-update-file-contents vhdl-speedbar-update-current-unit message "Updating hierarchy...done"] 3 (#$ . 444477)])
#@83 Get instantiation hierarchy beginning in architecture ARCH-KEY of
entity ENT-KEY.
(defalias 'vhdl-get-hierarchy #[(ent-alist conf-alist ent-key arch-key conf-key conf-inst-alist level indent &optional include-top ent-hier) "\306	\307#\203\306\310\n8\307#\202\311\310\n8!\211@A)\310
8\312\211\312\211 !\312\211\"#\312\211$%\312\211&'\312\211()\312\211*+,\313U\203Y\314\315!\210-\203c,T,	.\235\203o\316\317	\"\210\203\316
@\211@&\3208'\3218*/\211%\203\266%@@\322&D\235\203\255%@A@'\206\250\323\227\232\204\266%A\211%\204\221\320%@8\206\300**\3060*\307#!*\203\333!\204\333\324\325*\"\210\326%@8\206\374\310!8\206\374\310\3060\3218\307#8\206\374\3278(\306(\307#\310%@8\2069
\320!8\2069
\3308\2069
\320\3060\3218\"8\2069
\3208\2069
\3108\211@@))\306\3108)\307# \327%@8\206R
\3318+A@\3268\3108B@\206k
\3208A@\3268B @\206|
) A@\326 8B!@\206\215
*!A@\326!8B+,\257\n\"\3320()*\327!8,T1\312	.B&\n$\333#\"C$##A\211\204t-\203\364
\312\211\n@\nA@\326\n8B
@
A@\326
8B\312\211\211,S\257\n#B#,\313U\204-\203,\334U\203\314\323!\210#.\207" [ent-alist ent-key ent-entry arch-key x arch-entry aget t 3 last nil 0 message "Extract design hierarchy..." error "ERROR:  Instantiation loop detected, component instantiates itself: \"%s\"" 4 7 "all" "" vhdl-warning-when-idle "Configuration not found: \"%s\"" 2 5 6 8 vhdl-get-hierarchy append 1 inst-alist inst-entry inst-ent-entry inst-arch-entry inst-conf-entry comp-entry hier-list subcomp-list tmp-list inst-key inst-comp-name inst-ent-key inst-arch-key inst-conf-key inst-lib-key level include-top ent-hier conf-inst-alist conf-alist indent] 13 (#$ . 444883)])
#@43 Get all instantiations of entity ENT-KEY.
(defalias 'vhdl-get-instantiations #[(ent-key indent) "\306\307	!\310#\311\211\211\211\211\211\211\203\200@\312\f8\211\203w@\3128\211\203n@\313\n8\232\203e\nA@\314\n8\315\n8B\fA@\314\f8\315\f8BA@\3148\3158B\257
BA\211\2045A\211\204(A\211\204
\237.\207" [vhdl-entity-alist indent inst-entry arch-entry ent-entry ent-inst-list aget vhdl-speedbar-line-key t nil 4 5 2 3 inst-alist arch-alist ent-alist ent-key] 9 (#$ . 446649)])
#@44 Save all updated hierarchy caches to file.
(defalias 'vhdl-save-caches #[nil "\300\301\302\217\207" [nil (byte-code "\205!\303 \210	\304\305!\210\n\203\306\n@!\210\nA\211\204\304\307!)\207" [vhdl-speedbar-save-cache vhdl-updated-project-list project-list vhdl-update-hierarchy message "Saving hierarchy caches..." vhdl-save-cache "Saving hierarchy caches...done"] 3) ((error (byte-code "\300\301!\210\302\303!\207" [vhdl-warning "ERROR:  An error occurred while saving the hierarchy caches" sit-for 2] 2)))] 3 (#$ . 447176) nil])
#@39 Save current hierarchy cache to file.
(defalias 'vhdl-save-cache #[(key) "p	\306 	\307\310 !\311\312\313@B\314\315\316\206\317#\320\321 Q\"!A\322A
\"B\2061
C\203;\323\202<\324\325\326B!!\204N\327\326B!\330\"\210\331B!\204e\332\333\334\307B!\"!\210\335\336!\202\212
\337\340B\"\210\341B\330\211#q\210\342 \210\343\344\345A!\346D\347\261\210\350\203\214\351\202\215\352\353\261\210\203\233c\210\202\240\354
p\"\210\355\356\357!\321 \360\361\362D\363\350\203\265\323\202\266\324\364\365	\320\261\210\354\206\303
p\"\210\366c\210\367E\235\203Q
\370\371	\372\261\210\373\374FC\330#p\"\210\375\376	\372\261\210\373\374GC\330#p\"\210\377\201N	\372\261\210\373\374HC\330#p\"\210\201O\201P	\372\261\210\373\374IC\330#p\"\210\201Q\201R	\372\261\210\373\374JC\330#p\"\210\203N
\201S\201T	\372\261\210\373\374KC\330#p\"\210\366c\210\201UE\235\203s
\201V\201W	\372\261\210\373\374LC\330#p\"\210\366c\210\201XCM\"M\201Y \210\201Zp!\210q.	\207" [orig-buffer key vhdl-project project default-directory directory vhdl-project-p abbreviate-file-name vhdl-default-directory vhdl-resolve-env-variable vhdl-replace-string "\\(.*\\) \\(.*\\)" subst-char-in-string 32 95 "dir" " " user-login-name expand-file-name "project" "directory" file-exists-p file-name-directory make-directory t file-writable-p vhdl-warning format "File not writable: \"%s\"" sit-for 2 message "Saving cache: \"%s\"" find-file-noselect erase-buffer ";; -*- Emacs-Lisp -*-\n\n" ";;; " file-name-nondirectory " - design hierarchy cache file for Emacs VHDL Mode " "\n" "\n;; " "Project  " "Directory" " : " prin1 "\n;; Saved     : " format-time-string "%Y-%m-%d %T " "\n\n" "\n;; version number\n" "(setq vhdl-cache-version \"" "\")\n" " name" "\n(setq " ")\n" hierarchy "\n;; entity and architecture cache\n" "(aput 'vhdl-entity-alist " " '" print aget ")\n\n;; configuration cache\n" "(aput 'vhdl-config-alist " ")\n\n;; package cache\n" vhdl-speedbar-cache-file-name file-name file-dir-name cache-key vhdl-version vhdl-speedbar-save-cache vhdl-entity-alist vhdl-config-alist vhdl-package-alist vhdl-ent-inst-alist vhdl-file-alist vhdl-directory-alist vhdl-speedbar-shown-unit-alist vhdl-updated-project-list "(aput 'vhdl-package-alist " ")\n\n;; instantiated entities cache\n" "(aput 'vhdl-ent-inst-alist " ")\n\n;; design units per file cache\n" "(aput 'vhdl-file-alist " ")\n\n;; source directories in project cache\n" "(aput 'vhdl-directory-alist " display "\n;; shown design units cache\n" "(aput 'vhdl-speedbar-shown-unit-alist " delete save-buffer kill-buffer] 14 (#$ . 447720)])
#@45 Load hierarchy cache information from file.
(defalias 'vhdl-load-cache #[(key) "\306 \307\310\311\fB\312\313\314\315 \206\316#\317\320 Q\"!\321
\"\322\323>\2042\324\325\323\"\210\326!\205=\322\327\330\217.\207" [key vhdl-project default-directory directory vhdl-speedbar-cache-file-name file-name vhdl-default-directory vhdl-resolve-env-variable vhdl-replace-string "\\(.*\\) \\(.*\\)" subst-char-in-string 32 95 vhdl-project-p "dir" " " user-login-name expand-file-name nil vhdl-save-caches add-hook kill-emacs-hook file-exists-p (byte-code "\302!\210\303\304\305\306\307\"\310#\303\311\305	\307\"\310#\231\207" [file-dir-name vhdl-cache-version load-file mapconcat #[(a) "\301\302\303!\"\207" [a format "%3d" string-to-number] 4] split-string "3.33" "\\." "" #[(a) "\301\302\303!\"\207" [a format "%3d" string-to-number] 4]] 6) ((error (byte-code "\301\302\303\"!\210\304\207" [file-dir-name vhdl-warning format "ERROR:  Corrupted cache file: \"%s\"" nil] 4))) file-dir-name vhdl-cache-version] 7 (#$ . 450350)])
#@91 Make sure that hierarchy information is available.  Load cache or scan files
if required.
(defalias 'vhdl-require-hierarchy-info #[nil "\304 \203\305	\"\206\306!?\205-\307!\207\310\n!\305	\"\206%\306!?\205,\311!)\207" [vhdl-project vhdl-file-alist default-directory directory vhdl-project-p assoc vhdl-load-cache vhdl-scan-project-contents abbreviate-file-name vhdl-scan-directory-contents] 3 (#$ . 451395)])
#@54 Keymap used when in the VHDL hierarchy browser mode.
(defvar vhdl-speedbar-key-map nil (#$ . 451824))
#@49 Additional menu-items to add to speedbar frame.
(defvar vhdl-speedbar-menu-items nil (#$ . 451932))
#@22 Initialize speedbar.
(defalias 'vhdl-speedbar-initialize #[nil "\211\203!	\211@A)\306=\203\307	\211@@)!\210	A\211\204)\310\311!\205\220
\312\313!\210\312\314!\210\204\243\315 \316\317\320#\210\316\321\320#\210\316\322\323#\210\316\324\323#\210\316\325\326#\210\316\327\330#\210\316\331\332#\210\316\333\334#\210\316\335\336#\210\316\337\340#\210\316\341\342#\210\316\343\344#\210\316\345\346#\210\347\211\350X\203\242\316\351\f!\352\353\354\355\fDF#\210\fT\211\202\210)\316
\356\357#\210\316
\360\361#\210@\204O
\362\363\364\365\366\347\367A\211\350X\203\356\370\f\347U\203\317\371\202\322\351\f!\355\fD\372\373\374\375\376\fE\377\351\f!&ABA\fT\211\202\277A\237*\201E\201F\201G\201H\201I\201J\201K\201L\370\201M\344\201N\201O\201P\201QBBBBB\"\201L\370\201R\344\201N\201S\201P\201TBBBBB\"\201UBBBBBBBBBBBBBBB@\201V\201W!\210\201V\201X!\210\201Y\201ZB\"BC\201[=\203x
\201\\DC\201]=\203\206
\201^D\201_\201`\201a\"\207" [auto-mode-alist mode-alist x vhdl-speedbar-key-map key speedbar-mode-map vhdl-mode speedbar-add-supported-extension boundp speedbar-mode-functions-list speedbar-add-mode-functions-list ("vhdl directory" (speedbar-item-info . vhdl-speedbar-item-info) (speedbar-line-directory . speedbar-files-line-path)) ("vhdl project" (speedbar-item-info . vhdl-speedbar-item-info) (speedbar-line-directory . vhdl-speedbar-line-project)) speedbar-make-specialized-keymap define-key "e" speedbar-edit-line "
" "+" speedbar-expand-line "=" "-" vhdl-speedbar-contract-level "_" vhdl-speedbar-contract-all "C" vhdl-speedbar-port-copy "P" vhdl-speedbar-place-component "F" vhdl-speedbar-configuration "A" vhdl-speedbar-select-mra "K" vhdl-speedbar-make-design "R" vhdl-speedbar-rescan-hierarchy "S" vhdl-save-caches 0 9 int-to-string lambda nil (interactive) vhdl-speedbar-set-depth "h" #[nil "\300\301!\207" [speedbar-change-initial-expansion-list "vhdl directory"] 2 nil nil] "H" #[nil "\300\301!\207" [speedbar-change-initial-expansion-list "vhdl project"] 2 nil nil] ["Edit" speedbar-edit-line t] ["Expand" speedbar-expand-line (save-excursion (beginning-of-line) (looking-at "[0-9]+: *.\\+. "))] ["Contract" vhdl-speedbar-contract-level t] ["Expand All" vhdl-speedbar-expand-all t] ["Contract All" vhdl-speedbar-contract-all t] ("Hierarchy Depth") vector "All" :style radio :selected = vhdl-speedbar-hierarchy-depth :keys vhdl-speedbar-menu-items menu-list speedbar-stealthy-function-list vhdl-speedbar-display-mode speedbar-initial-expansion-list-name "--" ["Copy Port/Subprogram" vhdl-speedbar-port-copy (or (vhdl-speedbar-check-unit 'entity) (vhdl-speedbar-check-unit 'subprogram))] ["Place Component" vhdl-speedbar-place-component (vhdl-speedbar-check-unit 'entity)] ["Generate Configuration" vhdl-speedbar-configuration (vhdl-speedbar-check-unit 'architecture)] ["Select as MRA" vhdl-speedbar-select-mra (vhdl-speedbar-check-unit 'architecture)] ["Make" vhdl-speedbar-make-design (save-excursion (beginning-of-line) (looking-at "[0-9]+: *[[<]"))] ["Generate Makefile" vhdl-speedbar-generate-makefile (save-excursion (beginning-of-line) (looking-at "[0-9]+:"))] apply "Rescan Directory" :active (save-excursion (beginning-of-line) (looking-at "[0-9]+:")) :visible ((not vhdl-speedbar-show-projects)) "Rescan Project" (save-excursion (beginning-of-line) (looking-at "[0-9]+:")) (vhdl-speedbar-show-projects) (["Save Caches" vhdl-save-caches vhdl-updated-project-list]) speedbar-add-expansion-list ("vhdl directory" vhdl-speedbar-menu-items vhdl-speedbar-key-map vhdl-speedbar-display-directory) ("vhdl project" vhdl-speedbar-menu-items vhdl-speedbar-key-map vhdl-speedbar-display-projects) append (("vhdl directory" vhdl-speedbar-update-current-unit) ("vhdl project" vhdl-speedbar-update-current-project vhdl-speedbar-update-current-unit)) directory "vhdl directory" project "vhdl project" add-hook speedbar-timer-hook vhdl-update-hierarchy] 23 (#$ . 452038)])
#@22 Open/close speedbar.
(defalias 'vhdl-speedbar #[(&optional arg) "\300\301!\204\n\302\303!\207\304\305\306\217\207" [fboundp speedbar error "WARNING:  Speedbar is not available or not installed" nil (speedbar-frame-mode arg) ((error (error "WARNING:  An error occurred while opening speedbar")))] 3 (#$ . 455994) nil])
#@32 Name of last selected project.
(defvar vhdl-speedbar-last-selected-project nil (#$ . 456319))
#@53 Allow the buffer to be writable and evaluate FORMS.
(defalias 'speedbar-with-writable '(macro . #[(&rest forms) "\301\302\303BE\207" [forms let ((inhibit-read-only t)) progn] 4 (#$ . 456419)]))
(put 'speedbar-with-writable 'lisp-indent-function 0)
#@58 Display directory and hierarchy information in speedbar.
(defalias 'vhdl-speedbar-display-directory #[(directory depth &optional rescan) "\306\307	!\310\311!!\306\312\306\313\314\217)\207" [vhdl-speedbar-show-projects speedbar-ignored-directory-expressions speedbar-ignored-directory-regexp directory speedbar-last-selected-file inhibit-read-only nil speedbar-extension-list-to-regex abbreviate-file-name file-name-as-directory t (byte-code "\303	\"\210\304\305!	\"\210\306	\n#\210	\307U\205\310!\207" [directory depth speedbar-power-click speedbar-directory-buttons vhdl-speedbar-insert-dirs speedbar-file-lists vhdl-speedbar-insert-dir-hierarchy 0 vhdl-speedbar-expand-dirs] 4) ((error (vhdl-warning-when-idle "ERROR:  Invalid hierarchy information, unable to display correctly")))] 3 (#$ . 456674)])
#@57 Display projects and hierarchy information in speedbar.
(defalias 'vhdl-speedbar-display-projects #[(project depth &optional rescan) "\306\307\310\211\306\310\311\312\217\210)\310\211\207" [vhdl-speedbar-show-projects speedbar-ignored-directory-regexp speedbar-last-selected-file vhdl-speedbar-last-selected-project inhibit-read-only speedbar-full-text-cache t "." nil (vhdl-speedbar-insert-projects) ((error (vhdl-warning-when-idle "ERROR:  Invalid hierarchy information, unable to display correctly")))] 4 (#$ . 457495)])
#@34 Insert all projects in speedbar.
(defalias 'vhdl-speedbar-insert-projects #[nil "\306\307!\210\203\310\311	!!\202	\312\211\203;\313\314\315\316\211@@)\211@@)\317\211@@)\320\321&	\210A\211\204	\211\205n\211@@)
\235\203feb\210\322\323\211@@)\324Q\312\325#\203f\326\225b\210\327 \210A\211\204A\312*\207" [vhdl-project-sort vhdl-project-alist vhdl-speedbar-update-current-unit project-alist x vhdl-speedbar-shown-project-list vhdl-speedbar-make-title-line "Projects:" vhdl-sort-alist copy-alist nil speedbar-make-tag-line angle 43 vhdl-speedbar-expand-project vhdl-toggle-project speedbar-directory-face 0 re-search-forward "^\\([0-9]+:\\s-*<\\)[+]>\\s-+" "$" t 1 speedbar-do-function-pointer] 11 (#$ . 458031)])
#@99 Insert hierarchy of PROJECT.  Rescan directories if RESCAN is non-nil,
otherwise use cached data.
(defalias 'vhdl-speedbar-insert-project-hierarchy #[(project indent &optional rescan) "\204\306	\n\"\204\307	!\204\310	!\210\311\312	\313#\312\f	\313#\312
	\313#\312	\313#@%\210\314!\315\261\210\316`\317Z`S\320\313$\210\316`S`\320\321$\210\322	!\207" [rescan project vhdl-file-alist vhdl-entity-alist vhdl-config-alist vhdl-package-alist assoc vhdl-load-cache vhdl-scan-project-contents vhdl-speedbar-insert-hierarchy aget t int-to-string ":\n" put-text-property 3 invisible nil vhdl-speedbar-expand-units vhdl-ent-inst-alist indent] 8 (#$ . 458775)])
#@99 Insert hierarchy of DIRECTORY.  Rescan directory if RESCAN is non-nil,
otherwise use cached data.
(defalias 'vhdl-speedbar-insert-dir-hierarchy #[(directory depth &optional rescan) "\204\306	\n\"\204\307	!\204\310	!\210\311\312	\313#\312\f	\313#\312
	\313#\312	\313#@%\210\314	!\210\315\316	\211CC#\207" [rescan directory vhdl-file-alist vhdl-entity-alist vhdl-config-alist vhdl-package-alist assoc vhdl-load-cache vhdl-scan-directory-contents vhdl-speedbar-insert-hierarchy aget t vhdl-speedbar-expand-units aput vhdl-directory-alist vhdl-ent-inst-alist depth] 8 (#$ . 459446)])
#@60 Insert hierarchy of ENT-ALIST, CONF-ALIST, and PACK-ALIST.
(defalias 'vhdl-speedbar-insert-hierarchy #[(ent-alist conf-alist pack-alist ent-inst-list depth) "\204	\204\n\204\306\307\"\207\310\211\211\203!\306\311\"\210\203l@\312\313\314\315@A@\316\3178\3208B\321&	\210\3178\204S\322\210\323c\210\324u\210@\235\204e\322\210\325c\210\324u\210A\211\204%	\203u\306\326\"\210	\203\231	@\312\313\314\327
@
A@\316\317
8\320
8B\330&	\210	A\211\204y\n\203\242\306\331\"\210\n\205\310\n@\332\f@\fA@\317\f8\320\f8B\333\f8\334\f8B%\210\nA\211\204\246\310+\207" [ent-alist conf-alist pack-alist depth pack-entry conf-entry vhdl-speedbar-make-title-line "No VHDL design units!" nil "Entities:" speedbar-make-tag-line bracket 43 vhdl-speedbar-expand-entity vhdl-speedbar-find-file 2 3 vhdl-speedbar-entity-face 0 "!" 1 " (top)" "Configurations:" vhdl-speedbar-expand-config vhdl-speedbar-configuration-face "Packages:" vhdl-speedbar-make-pack-line 7 8 ent-entry ent-inst-list] 11 (#$ . 460044)])
#@65 Rescan hierarchy for the directory or project under the cursor.
(defalias 'vhdl-speedbar-rescan-hierarchy #[nil "\303\211\n\203\304 \305	!\210\202>\212\306 \210\307\310!)\203-\311\312\303\313#\210\314\315\316 !!\210\202>\316 \317\320\"\210\314\315\321\322\"!!\210\323	!*\207" [path key vhdl-speedbar-show-projects nil vhdl-speedbar-line-project vhdl-scan-project-contents beginning-of-line looking-at "[^0-9]" re-search-forward "[0-9]+:" t vhdl-scan-directory-contents abbreviate-file-name speedbar-line-directory string-match "^\\(.+[/\\]\\)" match-string 1 vhdl-speedbar-refresh] 5 (#$ . 461087) nil])
#@80 Expand subdirectories in DIRECTORY according to
 `speedbar-shown-directories'.
(defalias 'vhdl-speedbar-expand-dirs #[(directory) "\304!A\305\306!C\n\203.\307\n@!\203'\310 \210\311\312!\203'\313\225b\210\314 \210\nA\211\204*\301\305\315\"\207" [speedbar-shown-directories vhdl-speedbar-update-current-unit sf default-directory reverse nil expand-file-name speedbar-goto-this-file beginning-of-line looking-at "[0-9]+:\\s-*<" 0 speedbar-do-function-pointer t] 4 (#$ . 461708)])
#@93 Expand design units in directory/project KEY according to
`vhdl-speedbar-shown-unit-alist'.
(defalias 'vhdl-speedbar-expand-units #[(key) "\306	\307#\310\211\311\300	\"\210\307\312 p\313\216\314!\210\f\203\212\315	\f\211@@)\"\210\316 \210\f@A@\310\317\320!\203\203\321\225b\210`\322 \210\323!\210\203\203b\210\324\325@\326Q\310\307#\203z\316 \210\317\327!\203z\321\225b\210\322 \210\323!\210A\211\204T\fA*\202.\303\310\307\"\207" [vhdl-speedbar-shown-unit-alist key vhdl-updated-project-list vhdl-speedbar-update-current-unit unit-alist case-fold-search aget t nil adelete syntax-table ((byte-code "rq\210\302	!\210)\302\207" [#1=#:buffer #2=#:table set-syntax-table] 2)) set-syntax-table vhdl-speedbar-goto-this-unit beginning-of-line looking-at "^[0-9]+:\\s-*\\[" 0 speedbar-do-function-pointer select-frame re-search-forward "^[0-9]+:\\s-*\\(\\[\\|{.}\\s-+" "\\>\\)" "^[0-9]+:\\s-*{" #1# #2# vhdl-mode-ext-syntax-table x position arch-alist speedbar-frame] 5 (#$ . 462202)])
#@54 Contract current level in current directory/project.
(defalias 'vhdl-speedbar-contract-level #[nil "\212\300 \210\301\302!)\204(\212\300 \210\301\303!)\2051\304\305\306\307\310\311!!S\312]\"\313\314#\2051\312\225b\210\315 \210\316 \207" [beginning-of-line looking-at "^[0-9]:\\s-*[[{<]-" "^\\([0-9]+\\):" re-search-backward format "^[0-%d]:\\s-*[[{<]-" string-to-number match-string 1 0 nil t speedbar-do-function-pointer speedbar-center-buffer-smartly] 6 (#$ . 463230) nil])
#@66 Contract all expanded design units in current directory/project.
(defalias 'vhdl-speedbar-contract-all #[nil "\203\212\304 \210\305\306!)\203\307\310 \207\311 \312\313\n\"\210\310\205\"\n!\210\314>\205.\315\316\n\")\207" [vhdl-speedbar-show-projects vhdl-speedbar-shown-project-list key vhdl-speedbar-save-cache beginning-of-line looking-at "^0:" nil vhdl-speedbar-refresh vhdl-speedbar-line-key adelete vhdl-speedbar-shown-unit-alist display add-to-list vhdl-updated-project-list] 3 (#$ . 463715) nil])
#@55 Expand all design units in current directory/project.
(defalias 'vhdl-speedbar-expand-all #[nil "\306 \307	\310#\307\310#\307
\310#\311\211\311\312\313\"\210\n\203b\314\n@8\311\203L\211@@)BA\211\2046\n\211@@)DB\nA\211\204(\f\203z\f\211@@)CB\fA\211\204f\203\226\211@@)CBA\211\204\315\316#\210\317 \210\320>\205\253\312\321\".\207" [key vhdl-entity-alist ent-alist vhdl-config-alist conf-alist vhdl-package-alist vhdl-speedbar-line-key aget t nil add-to-list vhdl-speedbar-shown-project-list 4 aput vhdl-speedbar-shown-unit-alist vhdl-speedbar-refresh display vhdl-updated-project-list pack-alist arch-alist unit-alist subunit-alist x vhdl-speedbar-save-cache] 5 (#$ . 464236) nil])
#@47 Expand/contract the project under the cursor.
(defalias 'vhdl-speedbar-expand-project #[(text token indent) "\306\307\"\203)\310\311!\210	\n\235\204	\nB\312\212\313\210\314u\210\315	\fT
#\210*\202D\306\316\"\203@\310\317!\210\320	\n\"\321\f!\210\202D\322\323!\210\324 \232\205N\325 \207" [text token vhdl-speedbar-shown-project-list inhibit-read-only indent speedbar-power-click string-match "+" speedbar-change-expand-button-char 45 t nil 1 vhdl-speedbar-insert-project-hierarchy "-" 43 delete speedbar-delete-subblock error "Nothing to display" selected-frame speedbar-center-buffer-smartly speedbar-frame] 4 (#$ . 465004)])
#@46 Expand/contract the entity under the cursor.
(defalias 'vhdl-speedbar-expand-entity #[(text token indent) "\306\307\"\203$
\310	!\311\n\312#\311\f
\312#1\313182\314
	\"3\3151842G\316V5\317\211672\204M3\204M4\204M\320\321!\210\202
\320\322!\210\311\n\312#\323\324
\317#\210\323\325\n#\210)\3128\212\317\210\316u\2102\203|\326\327	T\"\2102\203\3052@6\330\331\332\333
6@B6A@\334\33568\31368B\336	T&	\2105\203\2746@\33718\232\203\274\340\210\341c\210\316u\2102A\2112\204\2013\203\320\326\342	T\"\2103\203
3@7\3437@7A@\33578\31378\33778\31578\317\211\211	T\340\344&\f\2103A\2113\204\325\3454	T	#\210*\3469>\203
\347\350\n\"\210\351\312\211\"\210.	\202l
\306\352\"\203h
\320\332!\210\310	!\311\n\312#\353\324
\"\210\203O
\323\325\n#\210\202T
\353\325\n\"\210\354	!\210\3469>\203d
\347\350\n\"\210*\202l
\355\356!\210\357 :\232\205v
\360 \207" [text indent key vhdl-entity-alist ent-alist token string-match "+" vhdl-speedbar-line-key aget t 3 vhdl-get-instantiations 5 1 nil speedbar-change-expand-button-char 63 45 aput unit-alist vhdl-speedbar-shown-unit-alist vhdl-speedbar-make-title-line "Architectures:" speedbar-make-tag-line curly 43 vhdl-speedbar-expand-architecture vhdl-speedbar-find-file 2 vhdl-speedbar-architecture-face 4 0 " (mra)" "Instantiated as:" vhdl-speedbar-make-inst-line " in " vhdl-speedbar-insert-subpackages display add-to-list vhdl-updated-project-list vhdl-speedbar-update-current-unit "-" adelete speedbar-delete-subblock error "Nothing to display" selected-frame speedbar-center-buffer-smartly ent-entry arch-alist inst-alist subpack-alist multiple-arch arch-entry inst-entry inhibit-read-only vhdl-speedbar-save-cache speedbar-frame] 14 (#$ . 465652)])
#@52 Expand/contract the architecture under the cursor.
(defalias 'vhdl-speedbar-expand-architecture #[(text token indent) "\306\307\"\203
\310	S!\311\n\312#\311
\n\312#.\313\f./@/A\314\211\315	S&0\311\f/@\312#1\311\31618/A\312#2\317283\31440\204[3\204[\320\321!\210\202
\320\322!\210\311\n\312#\311/@\312#@5\323\324/@/A5BC#\210\323\325\n#\210*\3126\212\314\210\326u\2100\203\235\327\330	T\"\2100\203\3600@47\315U\204\270\331487W\203\347\3324@4A@\33348\31648\31748\33448\33548\33648\33748	T\33148T\340&\f\2100A\2110\204\242\3413	T	S#\210*\3428>\203
\343\344\n\"\210\345\312\211\"\210.\202a
\306\346\"\203]
\320\347!\210\310	S!\311\n\312#\311/@\312#@5\323\324/@\350/A5\"C#\210\323\325\n#\210\351	!\210\3428>\203Y
\343\344\n\"\210+\202a
\352\353!\210\354 9\232\205k
\355 \207" [text indent key vhdl-entity-alist ent-alist vhdl-config-alist string-match "+" vhdl-speedbar-line-key aget t vhdl-get-hierarchy nil 0 3 4 speedbar-change-expand-button-char 63 45 aput unit-alist vhdl-speedbar-shown-unit-alist 1 vhdl-speedbar-make-title-line "Subcomponent hierarchy:" 9 vhdl-speedbar-make-inst-line 2 5 6 7 8 ": " vhdl-speedbar-insert-subpackages display add-to-list vhdl-updated-project-list vhdl-speedbar-update-current-unit "-" 43 delete speedbar-delete-subblock error "Nothing to display" selected-frame speedbar-center-buffer-smartly conf-alist token hier-alist ent-entry arch-entry subpack-alist entry arch-alist inhibit-read-only vhdl-speedbar-hierarchy-depth vhdl-speedbar-save-cache speedbar-frame] 14 (#$ . 467415)])
#@53 Expand/contract the configuration under the cursor.
(defalias 'vhdl-speedbar-expand-config #[(text token indent) "\306\307\"\203\361\310	!\311\n\312#\311\f
\".\311/\n\312#0\3130\f\314.8\315.8
\316.8\317	\312&	1\320.82\32131\204Q2\204Q\322\323!\210\202\354\322\324!\210\311\n\312#\325\326
\321#\210\325\327\n#\210)\3124\212\321\210\330u\2101\203\200\331\332	T\"\2101\203\3221@35\317U\204\233\333385X\203\311\3343@3A@\33538\31438\31538\31638\32038\33638\33738	T\33338\340&\f\2101A\2111\204\205\3412	T	#\210*\3426>\203\347\343\344\n\"\210\345\312\211\"\210.\2029
\306\346\"\2035
\322\347!\210\310	!\311\n\312#\350\326
\"\210\203
\325\327\n#\210\202!
\350\327\n\"\210\351	!\210\3426>\2031
\343\344\n\"\210*\2029
\352\353!\210\354 7\232\205C
\355 \207" [text indent key vhdl-config-alist conf-alist token string-match "+" vhdl-speedbar-line-key aget t vhdl-get-hierarchy 3 4 5 0 6 nil speedbar-change-expand-button-char 63 45 aput unit-alist vhdl-speedbar-shown-unit-alist 1 vhdl-speedbar-make-title-line "Design hierarchy:" 9 vhdl-speedbar-make-inst-line 2 7 8 ": " vhdl-speedbar-insert-subpackages display add-to-list vhdl-updated-project-list vhdl-speedbar-update-current-unit "-" 43 adelete speedbar-delete-subblock error "Nothing to display" selected-frame speedbar-center-buffer-smartly conf-entry vhdl-entity-alist ent-alist hier-alist subpack-alist entry inhibit-read-only vhdl-speedbar-hierarchy-depth vhdl-speedbar-save-cache speedbar-frame] 14 (#$ . 469019)])
#@47 Expand/contract the package under the cursor.
(defalias 'vhdl-speedbar-expand-package #[(text token indent) "\306\307\"\203
\310	!\311\n\312#\311\f
\312#.\313.8/\314.80\315.81\316\317.8\320.8\"2\321\21134\3215/\204U0\204U2\204U\322\323!\210\202
\322\324!\210\311\n\312#\325\326
\321#\210\325\327\n#\210)\3126\212\321\210\330u\210/\203\204\331\332	T\"\210/\203\264/@3\333\321\211\211
3@B3A@\334\33538\31338B\336	T&	\210/A\211/\204\2110\203\277\331\337	T\"\2100\203\3760@4\31114@\312#5\33548\203\365\3404A@\33548\31348B5A@\33558B	T$\2100A\2110\204\304\3412	T	#\210*\3427>\203
\343\344\n\"\210\345\312\211\"\210.\n\202e
\306\346\"\203a
\322\347!\210\310	!\311\n\312#\350\326
\"\210\203H
\325\327\n#\210\202M
\350\327\n\"\210\351	!\210\3427>\203]
\343\344\n\"\210*\202e
\352\353!\210\354 8\232\205o
\355 \207" [text indent key vhdl-package-alist pack-alist token string-match "+" vhdl-speedbar-line-key aget t 3 4 8 append 5 9 nil speedbar-change-expand-button-char 63 45 aput unit-alist vhdl-speedbar-shown-unit-alist 1 vhdl-speedbar-make-title-line "Components:" speedbar-make-tag-line vhdl-speedbar-find-file 2 vhdl-speedbar-entity-face "Subprograms:" vhdl-speedbar-make-subprogram-line vhdl-speedbar-insert-subpackages display add-to-list vhdl-updated-project-list vhdl-speedbar-update-current-unit "-" 43 adelete speedbar-delete-subblock error "Nothing to display" selected-frame speedbar-center-buffer-smartly pack-entry comp-alist func-alist func-body-alist subpack-alist comp-entry func-entry func-body-entry inhibit-read-only vhdl-speedbar-save-cache speedbar-frame] 11 (#$ . 470561)])
#@27 Insert required packages.
(defalias 'vhdl-speedbar-insert-subpackages #[(subpack-alist indent dir-indent) "\306\307	!\310#\311\211\311\203\312\313\"\210\205Z\211@A)\211@@)\306\n\310#\314
@\206=\f
A@\315
8B\316
8\317
8B%\210A\211\204\311,\207" [vhdl-package-alist dir-indent pack-alist pack-key lib-name pack-entry aget vhdl-speedbar-line-key t nil vhdl-speedbar-make-title-line "Packages Used:" vhdl-speedbar-make-subpack-line 2 6 7 subpack-alist indent x] 8 (#$ . 472238)])
#@59 Non-nil means to run `vhdl-speedbar-update-current-unit'.
(defvar vhdl-speedbar-update-current-unit t (#$ . 472755))
#@45 Highlight project that is currently active.
(defalias 'vhdl-speedbar-update-current-project #[nil "\203\206	\n\232\204\206\306\303!\203\206\307!\203\206\310 \f\311\312!\210\313\212\203ueb\210\314\315\211@@)\316Q\311\313#\203l\317\320\224\320\225\321\211@@)\n\232\203X\322\202Y\323$\210\211@@)\n\232\203l\320\224SA\211\204,)
\203}
b\210)\312!\210\n+\313\207" [vhdl-speedbar-show-projects vhdl-speedbar-last-selected-project vhdl-project speedbar-frame vhdl-project-alist pos boundp frame-live-p selected-frame nil select-frame t re-search-forward "<.> \\(" "\\)$" put-text-property 1 face speedbar-selected-face speedbar-directory-face project-alist last-frame inhibit-read-only x] 7 (#$ . 472878)])
#@121 Highlight all design units that are contained in the current file.
NO-POSITION non-nil means do not re-position cursor.
(defalias 'vhdl-speedbar-update-current-unit #[(&optional no-position always) "\306 \307\211\211\310\311!\203\312\313\314\315\"!\210\202 \316/!\210\317\320 \206'\321!0\203 
1\204:	2\232\204 
3\203U\f\203_\322\3234\f@\324#\"\fA\211\202@\3234\3175!\324#\316\f!\2106q\210\324\21178\325 p9:\326\216\327;!\210\212\3232\324#<\330\331<@2\332$\210\330\333<A@2\334$\210\330\331\335<82\336$\210\330\337\340<82\341$\210\330\342\3432\341$\210\330\344\345<82\346$\210)\323	\324#<\330\331<@	\347\n%\330\333<A@	\350\n%\330\331\335<8	\351\n%\330\337\340<8	\352\n%\330\342\353	\352\n%\330\344\345<8	\354\n%.\n\203
=\204
\nb\210\355 \210\356 \210	2\316
!\210-\324\207" [vhdl-speedbar-shown-project-list file-name pos file-alist project-list last-frame selected-frame nil fboundp speedbar-select-attached-frame dframe-select-attached-frame dframe-current-frame speedbar-frame speedbar-mode select-frame abbreviate-file-name buffer-file-name "" append aget t syntax-table ((byte-code "rq\210\302	!\210)\302\207" [#1=#:buffer #2=#:table set-syntax-table] 2)) set-syntax-table vhdl-speedbar-update-units "\\[.\\] " vhdl-speedbar-entity-face "{.} " vhdl-speedbar-architecture-face 3 vhdl-speedbar-configuration-face "[]>] " 4 vhdl-speedbar-package-face "\\[.\\].+(" ("body") "> " 6 vhdl-speedbar-instantiation-face vhdl-speedbar-entity-selected-face vhdl-speedbar-architecture-selected-face vhdl-speedbar-configuration-selected-face vhdl-speedbar-package-selected-face ("body") vhdl-speedbar-instantiation-selected-face speedbar-center-buffer-smartly speedbar-position-cursor-on-line speedbar-attached-frame vhdl-speedbar-update-current-unit always speedbar-last-selected-file vhdl-speedbar-show-projects vhdl-file-alist default-directory speedbar-buffer inhibit-read-only case-fold-search #1# #2# vhdl-mode-ext-syntax-table file-entry no-position] 7 (#$ . 473627)])
#@42 Help function to highlight design units.
(defalias 'vhdl-speedbar-update-units #[(text unit-list file-name face &optional pos) "\2039eb\210\305	\306@\307R\310\311#\2032\n\312\313\224\314\"@\232\203\206%\315 \316\313\224\313\225\304\f$\210\202A\211\204\207" [unit-list text file-name pos face re-search-forward "\\(" "\\)\\>" nil t get-text-property 1 speedbar-token point-marker put-text-property] 6 (#$ . 475664)])
#@29 Insert instantiation entry.
(defalias 'vhdl-speedbar-make-inst-line #[(inst-name inst-file-marker ent-name ent-file-marker arch-name arch-file-marker conf-name conf-file-marker lib-name depth offset delimiter) "`\306\307\n!\310\261\210\311	`\312\313$\210`\314\315\n_\"\210\f\316V\203;\317c\210\314\f\320U\203/\321\2020\315S\"\210\fS\211\202\311`\312\306$\210`\322c\210\323	`\306\211\211%\210`\324c\210`
\204`\325c\210\202n
c\210\323	`\326\327\330#&\210$c\210%\203\300`%c\210\323	`\331\327\330&&\210'\203\244\332c\210`'c\210\323	`\333\327\330(&\210\334c\210)\203\300\332c\210`)c\210\323	`\335\327\330*&\210\334c\210+\203\341+\336 \227\232\204\341`\332+\334\261\210\311\337	\\`S\340\341$\210\314\342\320\"\210\311`\312\306$*\207" [visible-start start depth speedbar-indentation-width offset inst-name nil int-to-string ":" put-text-property invisible t insert-char 32 0 "|" 1 45 ">" speedbar-make-button " " "(top)" vhdl-speedbar-instantiation-face speedbar-highlight-face vhdl-speedbar-find-file vhdl-speedbar-entity-face " (" vhdl-speedbar-architecture-face ")" vhdl-speedbar-configuration-face vhdl-work-library 2 face vhdl-speedbar-library-face 10 inst-file-marker delimiter ent-name ent-file-marker arch-name arch-file-marker conf-name conf-file-marker lib-name] 8 (#$ . 476102)])
#@23 Insert package entry.
(defalias 'vhdl-speedbar-make-pack-line #[(pack-key pack-name pack-file-marker body-file-marker depth) "`\306\307\n!\310\261\210\311	`\312\313$\210`\314\315\n_\"\210\311`\312\306$\210`\316c\210\317	`\320\321\322\f&\210`\314\315\323\306#\210`
c\210\317	`\324\321\325&\210@\204R\326c\210@\203n\327c\210`\330c\210\317	`\324\321\325&\210\331c\210\314\332\323\"\210\311`\312\306$*\207" [visible-start start depth speedbar-indentation-width pack-key pack-name nil int-to-string ":" put-text-property invisible t insert-char 32 "[+]" speedbar-make-button speedbar-button-face speedbar-highlight-face vhdl-speedbar-expand-package 1 vhdl-speedbar-package-face vhdl-speedbar-find-file "!" " (" "body" ")" 10 pack-file-marker body-file-marker] 7 (#$ . 477439)])
#@28 Insert used package entry.
(defalias 'vhdl-speedbar-make-subpack-line #[(pack-name lib-name pack-file-marker pack-body-file-marker depth) "`\306\307\n!\310\261\210\311	`\312\313$\210`\314\315\n_\"\210\311`\312\306$\210`\316c\210\317	`\306\211\211%\210`\320c\210`\fc\210\317	`\321\322\323
&\210@\203_\324c\210`\325c\210\317	`\321\322\323&\210\326c\210`\324\326\261\210\311\327	\\`S\330\331$\210\314\332\333\"\210\311`\312\306$*\207" [visible-start start depth speedbar-indentation-width pack-name pack-file-marker nil int-to-string ":" put-text-property invisible t insert-char 32 ">" speedbar-make-button " " vhdl-speedbar-package-face speedbar-highlight-face vhdl-speedbar-find-file " (" "body" ")" 2 face vhdl-speedbar-library-face 10 1 pack-body-file-marker lib-name] 7 (#$ . 478242)])
#@26 Insert subprogram entry.
(defalias 'vhdl-speedbar-make-subprogram-line #[(func-name func-file-marker func-body-file-marker depth) "`\306\307\n!\310\261\210\311	`\312\313$\210`\314\315\n_\"\210\311`\312\306$\210`\316c\210\317	`\306\211\211%\210`\320c\210`\fc\210\317	`\321\322\323
&\210@\203_\324c\210`\325c\210\317	`\321\322\323&\210\326c\210\314\327\330\"\210\311`\312\306$*\207" [visible-start start depth speedbar-indentation-width func-name func-file-marker nil int-to-string ":" put-text-property invisible t insert-char 32 ">" speedbar-make-button " " vhdl-speedbar-subprogram-face speedbar-highlight-face vhdl-speedbar-find-file " (" "body" ")" 10 1 func-body-file-marker] 7 (#$ . 479059)])
#@33 Insert design unit title entry.
(defalias 'vhdl-speedbar-make-title-line #[(text &optional depth) "`\305\n\203\306\n!\307\261\210\310	`\311\312$\210`\313\314\n\206\315_\"\210`\fc\210\316	`\305\211\211\211&\210\313\317\320\"\210\310`\311\305$*\207" [visible-start start depth speedbar-indentation-width text nil int-to-string ":" put-text-property invisible t insert-char 32 0 speedbar-make-button 10 1] 7 (#$ . 479781)])
#@24 Insert subdirectories.
(defalias 'vhdl-speedbar-insert-dirs #[(files level) "@\211\205\303\304\305\306	@	@\307\310\311\n&	\210	A\211\204\310)\207" [files dirs level speedbar-make-tag-line angle 43 vhdl-speedbar-dired speedbar-dir-follow nil speedbar-directory-face] 11 (#$ . 480220)])
#@71 Speedbar click handler for directory expand button in hierarchy mode.
(defalias 'vhdl-speedbar-dired #[(text token indent) "\306\307\"\203I\310\311	!\n\312Q!B\313\314!\210\315 \210\316\212\317\210\320u\210\321\322\311	!\n\312Q!	T\"\210\315 \210\323\324\311	!\n\312Q!	T
#\210*\325\316\211\"\210\202\231\306\326\"\203\225\315 \210\317\310\311	!\nP! \211!\203\205\306\327\330!P!@\"\204|!@ B !A\211!\204f \237+\313\331!\210\332	!\210\202\231\333\334!\210\335 \"\232\205\243\336 \207" [text indent token speedbar-shown-directories inhibit-read-only speedbar-power-click string-match "+" expand-file-name speedbar-line-directory "/" speedbar-change-expand-button-char 45 speedbar-reset-scanners t nil 1 vhdl-speedbar-insert-dirs speedbar-file-lists vhdl-speedbar-insert-dir-hierarchy abbreviate-file-name vhdl-speedbar-update-current-unit "-" "^" regexp-quote 43 speedbar-delete-subblock error "Nothing to display" selected-frame speedbar-center-buffer-smartly td newl oldl speedbar-frame] 6 (#$ . 480518)])
#@54 Derive and display information about this line item.
(defalias 'vhdl-speedbar-item-info #[nil "\212\302 \210\303\304!\203\305\225b\210\303\306!\203&\203!\307\310\311\312!\"\202\275\313 \202\275\303\314!\203\272\312\225b\210\315`\301\"\307\316	\317=\204C	\320=\203S\321\322!\323\232\203O\324\202\236\325\202\236	\326=\204_	\327=\203c\330\202\236	\331=\204o	\332=\203s\333\202\236	\334=\204	\335=\203\203\336\202\236	\337=\204\217	\340=\203\223\341\202\236	\342=\203\235\343\202\236\344\345\303\346!\210\312\224\312\225\"\347\315`\350\"@\206\262\351\352 \"$)\202\275\307\344!)\207" [vhdl-speedbar-show-projects face beginning-of-line looking-at "^[0-9]+:" 0 "\\s-*<[-+?]>\\s-+\\([^\n]+\\)$" message "Project \"%s\"" match-string-no-properties 1 speedbar-files-item-info "\\(\\s-*\\([[{][-+?][]}]\\|[| -]*>\\) \\)\"?\\w" get-text-property "%s \"%s\" in \"%s\"" vhdl-speedbar-entity-face vhdl-speedbar-entity-selected-face match-string 2 ">" "Component" "Entity" vhdl-speedbar-architecture-face vhdl-speedbar-architecture-selected-face "Architecture" vhdl-speedbar-configuration-face vhdl-speedbar-configuration-selected-face "Configuration" vhdl-speedbar-package-face vhdl-speedbar-package-selected-face "Package" vhdl-speedbar-instantiation-face vhdl-speedbar-instantiation-selected-face "Instantiation" vhdl-speedbar-subprogram-face "Subprogram" "" buffer-substring-no-properties "\"?\\(\\(\\w\\|_\\)+\\)\"?" file-relative-name speedbar-token "?" vhdl-default-directory] 8 (#$ . 481556)])
#@57 Calls `speedbar-line-text' and removes text properties.
(defalias 'vhdl-speedbar-line-text #[nil "\301 \302\303G\304$\210)\207" [string speedbar-line-text set-text-properties 0 nil] 5 (#$ . 483081)])
#@41 Get speedbar-line-text of higher level.
(defalias 'vhdl-speedbar-higher-text #[nil "\302\211\212\303 \210\304\305!\210\306\307\310!!\311\312\313	S\"\302\314#\205+\307\310!\315\316G\302$\210+\207" [string depth nil beginning-of-line looking-at "^\\([0-9]+\\):" string-to-number match-string 1 re-search-backward format "^%d: *[[<{][-+?][]>}] \\([^ \n]+\\)" t set-text-properties 0] 5 (#$ . 483291)])
#@52 Get currently displayed directory of project name.
(defalias 'vhdl-speedbar-line-key #[(&optional indent) "\203\302 \207\303\304\305	!!!\207" [vhdl-speedbar-show-projects indent vhdl-speedbar-line-project abbreviate-file-name file-name-as-directory speedbar-line-directory] 4 (#$ . 483704)])
#@39 Get currently displayed project name.
(defalias 'vhdl-speedbar-line-project #[(&optional indent) "\205\212\301\210\302\303\301\304#\210\305\306!)\207" [vhdl-speedbar-show-projects nil re-search-backward "^[0-9]+:\\s-*<[-+?]>\\s-+\\([^\n]+\\)$" t match-string-no-properties 1] 4 (#$ . 484005)])
#@40 Add file to `vhdl-modified-file-list'.
(defalias 'vhdl-add-modified-file #[nil "\203\n\301\302\303 \"\210\304\207" [vhdl-file-alist add-to-list vhdl-modified-file-list buffer-file-name nil] 3 (#$ . 484309)])
#@38 Resolve path wildcards in PATH-LIST.
(defalias 'vhdl-resolve-paths #[(path-list) "\306\211\211\211\211
\2035
@\307\310\"\210\311\312\313\"!\203&\fB\202.\314\315\312\313\"\"\210
A\211\204\f\203\246\f@\307\316\"\203\215\312\317\"\312\320\"\321\322\323\324\312\313\"\325\326\327\312\330\"!P#\306\211\203\201\311@!\203x@BA\211\204h*\"\fA\"\211\2026\307\331\"\210\311\312\313\"!\203\237B\fA\211\2049\237-\207" [dir path-end path-beg path-list-2 path-list-1 path-list nil string-match "\\(-r \\)?\\(\\([^?*]*[/\\]\\)*\\)" file-directory-p match-string 2 vhdl-warning-when-idle "No such directory: \"%s\"" "\\(-r \\)?\\(\\([^?*]*[/\\]\\)*\\)\\([^/\\]*[?*][^/\\]*\\)\\([/\\].*\\)" 1 5 append mapcar #[(var) "	\nQ\207" [path-beg var path-end] 3] vhdl-directory-files t "\\<" wildcard-to-regexp 4 "\\(-r \\)?\\(.*\\)[/\\].*" dir-list all-list] 12 (#$ . 484525)])
#@75 If UNIT is displayed in DIRECTORY, goto this line and return t, else nil.
(defalias 'vhdl-speedbar-goto-this-unit #[(directory unit) "`	\203\feb\210\202\304\n!\203$\305\306\307Q\310\311#\203$\312 \210\311\202(b\210\310)\207" [dest vhdl-speedbar-show-projects directory unit speedbar-goto-this-file re-search-forward "[]}] " "\\>" nil t speedbar-position-cursor-on-line] 4 (#$ . 485444)])
#@176 When user clicks on TEXT, load file with name and position in TOKEN.
Jump to the design unit if `vhdl-speedbar-jump-to-unit' is t or if the file
is already shown in a buffer.
(defalias 'vhdl-speedbar-find-file #[(text token indent) "@\204	\304\305!\207\306@!\307@!\210\n\204	\203&eb\210ASy\210\310 \210\311\312\211\"\210\313!\210\314 )\207" [token buffer vhdl-speedbar-jump-to-unit dframe-update-speed error "ERROR:  File cannot be found" get-file-buffer speedbar-find-file-in-frame recenter vhdl-speedbar-update-current-unit t speedbar-set-timer speedbar-maybee-jump-to-attached-frame] 3 (#$ . 485848)])
#@71 Copy the port of the entity/component or subprogram under the cursor.
(defalias 'vhdl-speedbar-port-copy #[nil "\301\302!\211\204\301\303!\204\304\305!\202'\306 \210\307\310!\203$\311\312\313\217\202'\304\314!)\207" [is-entity vhdl-speedbar-check-unit entity subprogram error "ERROR:  No entity/component or subprogram under cursor" beginning-of-line looking-at "\\([0-9]\\)+:\\s-*\\(\\[[-+?]\\]\\|>\\) \\(\\(\\w\\|\\s_\\)+\\)" info (byte-code "\305\306\224\307\"\211@\204$eb\210ASy\210\310\210	\203\311 \202U\312 \202U\313@!?\205Up\314@!\310\203>q\204E\310\315\316\217\203J\317\320\321\217\210\n\203R\322p!\210\fq+)\207" [token is-entity file-opened visiting-buffer source-buffer get-text-property 3 speedbar-token nil vhdl-port-copy vhdl-subprog-copy file-directory-p find-buffer-visiting (byte-code "\302@!q\210\303\304@!\210\305\306\307\310 #\210\305\311\312\310 #\210\305\313\312\310 #\210\305\314\315\310 #\210\303\207" [token file-opened create-file-buffer t vhdl-insert-file-contents modify-syntax-entry 45 ". 12" syntax-table 10 ">" 13 95 "w"] 4) ((error (byte-code "\203\303p!\210	q\210\304\305\n@\"\207" [file-opened source-buffer token kill-buffer error "ERROR:  File cannot be opened: \"%s\""] 3))) info (byte-code "eb\210ASy\210\302\210	\203\303 \210\202\304 \210\302\207" [token is-entity nil vhdl-port-copy vhdl-subprog-copy] 1) ((error (byte-code "\203\304p!\210	q\210\305\n\211A@)!\207" [file-opened source-buffer info x kill-buffer error] 3))) kill-buffer] 4) ((error (byte-code "\303\304\203\n\305\202\306	\211A@)#\207" [is-entity info x error "ERROR:  %s not scanned successfully\n  (%s)" "Port" "Interface"] 5))) "ERROR:  No entity/component or subprogram on current line"] 4 (#$ . 486469) nil])
#@59 Place the entity/component under the cursor as component.
(defalias 'vhdl-speedbar-place-component #[nil "\302\303!\204\n\304\305!\207\306 \210\307\310!\203\311\312\301\313\"!\210\202!\314!\210\315 \210\314	!\207" [speedbar-attached-frame speedbar-frame vhdl-speedbar-check-unit entity error "ERROR:  No entity/component under cursor" vhdl-speedbar-port-copy fboundp speedbar-select-attached-frame dframe-select-attached-frame dframe-current-frame speedbar-mode select-frame vhdl-compose-place-component] 4 (#$ . 488242) nil])
#@63 Generate configuration for the architecture under the cursor.
(defalias 'vhdl-speedbar-configuration #[nil "\303\304!\204\n\305\306!\207\307 \310 \311\312!\203 \313\314\315\316\"!\210\202$\317\n!\210\320	\"*\207" [ent-name arch-name speedbar-attached-frame vhdl-speedbar-check-unit architecture error "ERROR:  No architecture under cursor" vhdl-speedbar-line-text vhdl-speedbar-higher-text fboundp speedbar-select-attached-frame dframe-select-attached-frame dframe-current-frame speedbar-frame speedbar-mode select-frame vhdl-compose-configuration] 4 (#$ . 488780) nil])
#@50 Select the architecture under the cursor as MRA.
(defalias 'vhdl-speedbar-select-mra #[nil "\306\307!\204\n\310\311!\207\312 \227\313 \227\314\n\315 \206\316#\314\f	\316#\211\211AA)\211AA)\240\210\317 ,\207" [arch-key ent-key vhdl-entity-alist default-directory ent-alist ent-entry vhdl-speedbar-check-unit architecture error "ERROR:  No architecture under cursor" vhdl-speedbar-line-text vhdl-speedbar-higher-text aget vhdl-project-p t speedbar-refresh x] 5 (#$ . 489363) nil])
#@67 Make (compile) design unit or directory/project under the cursor.
(defalias 'vhdl-speedbar-make-design #[nil "\212\306 \210\307\310!)\204\311\312!\207\313\314!\315 \316 \317\320 \206\321 !\322\323!\2033\324\325\326\327\"!\210\2027\330\f!\210\331\205?\n!-\207" [directory vhdl-project unit-name is-unit speedbar-attached-frame default-directory beginning-of-line looking-at "[0-9]+: *\\(\\(\\[\\)\\|<\\)" error "ERROR:  No primary design unit or directory/project under cursor" match-string 2 vhdl-speedbar-line-text vhdl-speedbar-line-project file-name-as-directory speedbar-line-file speedbar-line-directory fboundp speedbar-select-attached-frame dframe-select-attached-frame dframe-current-frame speedbar-frame speedbar-mode select-frame vhdl-make] 5 (#$ . 489861) nil])
#@59 Generate Makefile for directory/project under the cursor.
(defalias 'vhdl-speedbar-generate-makefile #[nil "\302 \303\304 \206\n\305 !\306 *\207" [default-directory vhdl-project vhdl-speedbar-line-project file-name-as-directory speedbar-line-file speedbar-line-directory vhdl-generate-makefile] 3 (#$ . 490654) nil])
#@96 Check whether design unit under cursor corresponds to DESIGN-UNIT (or its
expansion function).
(defalias 'vhdl-speedbar-check-unit #[(design-unit) "\212\301 \210\302=\203\303\304\225\305\"\306>\2025\307=\203$\303\304\225\305\"\310>\2025\311=\2034\303\304\225\305\"\312=\2025\313)\207" [design-unit speedbar-position-cursor-on-line entity get-text-property 0 face (vhdl-speedbar-entity-face vhdl-speedbar-entity-selected-face) architecture (vhdl-speedbar-architecture-face vhdl-speedbar-architecture-selected-face) subprogram vhdl-speedbar-subprogram-face nil] 3 (#$ . 490980)])
#@60 Set hierarchy display depth to DEPTH and refresh speedbar.
(defalias 'vhdl-speedbar-set-depth #[(depth) "\302 \207" [depth vhdl-speedbar-hierarchy-depth speedbar-refresh] 1 (#$ . 491574)])
(byte-code "\301\302\303\304\305\306%\210\301\307\310\311\305\306%\210\301\312\313\314\305\306%\210\301\315\316\317\305\306%\210\301\320\321\322\305\306%\210\301\323\324\325\305\306%\210\301\326\327\330\305\306%\210\301\331\332\304\305\306%\210\301\333\334\311\305\306%\210\301\335\336\314\305\306%\210\301\337\340\317\305\306%\210\301\341\342\325\305\306%\210\343\344!\203k\345\346\347\217\210\350\300!\204y\351\352\353\"\210\202\203\353 \210\203\203\354 \210\345\207" [speedbar-frame custom-declare-face vhdl-speedbar-entity-face ((((class color) (background light)) (:foreground "ForestGreen")) (((class color) (background dark)) (:foreground "PaleGreen"))) "Face used for displaying entity names." :group speedbar-faces vhdl-speedbar-architecture-face ((((min-colors 88) (class color) (background light)) (:foreground "Blue1")) (((class color) (background light)) (:foreground "Blue")) (((class color) (background dark)) (:foreground "LightSkyBlue"))) "Face used for displaying architecture names." vhdl-speedbar-configuration-face ((((class color) (background light)) (:foreground "DarkGoldenrod")) (((class color) (background dark)) (:foreground "Salmon"))) "Face used for displaying configuration names." vhdl-speedbar-package-face ((((class color) (background light)) (:foreground "Grey50")) (((class color) (background dark)) (:foreground "Grey80"))) "Face used for displaying package names." vhdl-speedbar-library-face ((((class color) (background light)) (:foreground "Purple")) (((class color) (background dark)) (:foreground "Orchid1"))) "Face used for displaying library names." vhdl-speedbar-instantiation-face ((((class color) (background light)) (:foreground "Brown")) (((min-colors 88) (class color) (background dark)) (:foreground "Yellow1")) (((class color) (background dark)) (:foreground "Yellow"))) "Face used for displaying instantiation names." vhdl-speedbar-subprogram-face ((((class color) (background light)) (:foreground "Orchid4")) (((class color) (background dark)) (:foreground "BurlyWood2"))) "Face used for displaying subprogram names." vhdl-speedbar-entity-selected-face ((((class color) (background light)) (:foreground "ForestGreen" :underline t)) (((class color) (background dark)) (:foreground "PaleGreen" :underline t))) vhdl-speedbar-architecture-selected-face ((((min-colors 88) (class color) (background light)) (:foreground "Blue1" :underline t)) (((class color) (background light)) (:foreground "Blue" :underline t)) (((class color) (background dark)) (:foreground "LightSkyBlue" :underline t))) vhdl-speedbar-configuration-selected-face ((((class color) (background light)) (:foreground "DarkGoldenrod" :underline t)) (((class color) (background dark)) (:foreground "Salmon" :underline t))) vhdl-speedbar-package-selected-face ((((class color) (background light)) (:foreground "Grey50" :underline t)) (((class color) (background dark)) (:foreground "Grey80" :underline t))) vhdl-speedbar-instantiation-selected-face ((((class color) (background light)) (:foreground "Brown" :underline t)) (((class color) (background dark)) (:foreground "Yellow" :underline t))) fboundp speedbar nil (byte-code "\203(\303\301!\203\304	!\204(\305\306!\210\307\310!\203$\311\312\301\313\"!\210\202(\314\n!\210\303\207" [vhdl-speedbar-auto-open speedbar-frame speedbar-attached-frame boundp frame-live-p speedbar-frame-mode 1 fboundp speedbar-select-attached-frame dframe-select-attached-frame dframe-current-frame speedbar-mode select-frame] 4) ((error (vhdl-warning-when-idle "ERROR:  An error occurred while opening speedbar"))) boundp add-hook speedbar-load-hook vhdl-speedbar-initialize vhdl-speedbar-refresh] 6)
#@44 Return the name of the components package.
(defalias 'vhdl-get-components-package-name #[nil "\302 \211\203\303	@\304\305\306#\"\202	A)\207" [project vhdl-components-package-name vhdl-project-p vhdl-replace-string subst-char-in-string 32 95] 7 (#$ . 495427)])
#@51 Create entity and architecture for new component.
(defalias 'vhdl-compose-new-component #[nil "\306\307\310\311	#A\312\232\203\307\313\311	#\202\314\n\"\311\211@\311\211AB\311\211CD\315\316\n\f#\210E\317=\204e\314F\n\306#\320\321\322 !Q\323
!\203Z\324\325
\326Q!\204Z\327\330!\210\331
!\210\332 \210\333\311!\210G\203v\334 \210`Ddb\210\202|\335 \210\336c\210\337 \210H\203\216\340c\210\341\342 \343 \"\210\336c\210\335 \210\336c\210\344\345!\210\nc\210\344\346!\210I\347>\203\254\340c\210Jj\210\344\350!\210J\351_j\210\352c\210I\353>\203\307\340c\210Jj\210\344\354!\210J\351_j\210\352c\210I\355>\203\342\340c\210\344\356!\210\357\360!\204\360\344\345!\210\n\361\261\210\335 \210\340c\210E\362=\204
\340c\210\202Y
D\206
eb\210pA\314K\n\363\fQ\306#\320\321\322 !Q@\323@!\2039
\324\325@\326Q!\2049
\327\330!\210\331@!\210\332 \210\333\311!\210G\203S
\334 \210db\210\202Y
\335 \210\336c\210\344\364!\210\fc\210\344\365!\210\nc\210\344\366!\210Jj\210\335 \210\340c\210Jj\210\367c\210Jj\210\335 \210\336c\210H\204\253
\370 \204\253
Jj\210\335 \210\340c\210Jj\210\371c\210Jj\210\335 \210\336c\210\344\372!\210L\203\304
\373c\210\357\360!\204\301
\344\364!\210\fc\210\336c\210Jj\210\335 \210\340c\210Jj\210\374c\210Jj\210\335 \210\336c\210\344\356!\210\357\360!\204\360
\344\364!\210\f\361\261\210G\203M\312\232\204\375 \210\202
\335 \210\340c\210D\206eb\210pBA\203$Aq\210\376 \210Bq\210\376 \210\315\377\201N\201O\n\f#
\205B\201N\201P
\"@\205P\201N\201P@\"Q\".	\207" [case-fold-search vhdl-minibuffer-local-map ent-name vhdl-compose-architecture-name arch-name ent-file-name t read-from-minibuffer "entity name: " nil "" "architecture name: " vhdl-replace-string message "Creating component \"%s(%s)\"..." none "." file-name-extension buffer-file-name file-exists-p y-or-n-p "File \"" "\" exists; overwrite? " error "ERROR:  Creating component...aborted" find-file erase-buffer set-buffer-modified-p vhdl-template-header vhdl-comment-display-line "\n\n" vhdl-template-package-std-logic-1164 "\n" vhdl-template-standard-package vhdl-work-library vhdl-get-components-package-name vhdl-insert-keyword "ENTITY " " IS\n" (unit all) "GENERIC (\n" 2 ");\n" (unit all) "PORT (\n" (unit all) "END " vhdl-standard-p 87 ";\n\n" separate " " "ARCHITECTURE " " OF " " IS\n\n" "-- Internal signal declarations\n" vhdl-use-direct-instantiation "-- Component declarations\n" "BEGIN" "  -- " "-- Component instantiations\n" vhdl-template-footer save-buffer "%s" arch-file-name ent-buffer arch-buffer project end-pos vhdl-compose-create-files vhdl-entity-file-name vhdl-compose-include-header vhdl-use-components-package vhdl-insert-empty-lines vhdl-basic-offset vhdl-architecture-file-name vhdl-self-insert-comments vhdl-file-footer format "Creating component \"%s(%s)\"...done" "\n  File created: \"%s\""] 8 (#$ . 495699) nil])
#@99 Place new component by pasting current port as component declaration and
component instantiation.
(defalias 'vhdl-compose-place-component #[nil "\204\306\307!\207\212\310\311 \312\211\211\3137!\210\314\315!\203I\315 \316@A\"\211\203I@\317\320	!>\203B	\nB\321	\317\312#\210A\211\204-\322\216\323\324\312\310#\204_\325\324\312\310#\204_\306\326!\210\327\330!8\33198\310#\332\333\334 !Q:p;\335\336@\"\210<\204\253\337 \204\253\212\325\340@\341Q\312\310#)\204\253\325\342\312\"\210\343 \210\344\312x\210\345c\210=j\210\346\310!\210\325\347\312\"\210\343 \210\344\312x\210\345c\210=j\210\350\312\310\211#\210\3518\203
\352:!\203\326\353:!\210eb\210\325\3548\355Q\312\310#\204\353\306\3568\"\210\357\224b\210\212\323\360\312\310#)\203\n
\327\330!\203\n
\357\225b\210\343\361!\210\202
\362c\210\363u\210\364 \210\365;!\210\335\366@\".\n\207" [vhdl-port-list overlay overlay-intangible-list overlay-all-list current-syntax-table case-fold-search error "ERROR:  No port has been read" t syntax-table nil set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) re-search-backward "^architecture[ 	\n
\f]+\\w+[ 	\n
\f]+of[ 	\n
\f]+\\(\\w+\\)[ 	\n
\f]+is\\>" re-search-forward "ERROR:  No architecture found" match-string 1 vhdl-replace-string "." file-name-extension buffer-file-name message "Placing component \"%s\"..." vhdl-use-direct-instantiation "^\\s-*component\\s-+" "\\>" "^begin\\>" beginning-of-line " 	\n
\f" "\n\n" vhdl-port-paste-component "^end\\>" vhdl-port-paste-instance 3 file-exists-p find-file "^entity[ 	\n
\f]+" "[ 	\n
\f]+is\\>" "ERROR:  Entity not found: \"%s\"" 0 "^\\(library\\|use\\)\\|end\\>" 2 "\n" -1 vhdl-port-paste-context-clause switch-to-buffer "Placing component \"%s\"...done" vhdl-mode-ext-syntax-table ent-name vhdl-entity-file-name ent-file-name orig-buffer vhdl-use-components-package vhdl-basic-offset] 6 (#$ . 498597) nil])
#@21 Connect components.
(defalias 'vhdl-compose-wire-components #[nil "\212\306\307 \310\211\211\311
!\210\312\313!\203@\313 \314\n@\nA\"\211\203@\n@\315\316!>\2039	B\317\315\310#\210\nA\211\204$\320\216\321\322\310\306#\204V\323\322\310\306#\204V\324\325!\210\326\327!@\330A@\306#\331\332\333 !QB\334 C\323\335\310\"D\323\336\310\"E\337 F\330GF\306#\331\332\333 !QH\310\211IJ\310\211KL\310\211MN\310\211OP\310\211QR\310\211ST\310\211UV\310\211WX\310\211YZ\310\211[\\\310\211]^\310\211_`\310\211ab\310\211cd\310\211ef\310\211gh\310\211ij\310\211kl\340\341!\210Db\210\323\342E\306#\203\367\343\327!I\343\344!J\343\345!K\326\346!\206\"
\326\347!MJ\203\225
m\2033
H\204P
\212eb\210\323\350J\351Q\310\306#\204I
\324\352J\"\210\353 \210)\202\375
\354m\205X
H!\204\375
p\355m\205e
H!\310nopo\203x
oq\204
\310\356\357\217\203\204
\360\361\362\217\210n\203\215
\363p!\210pq\210+\202\375
\330AK\306#\331\332\333 !Q\211L\204\305
\212eb\210\323\364K\351Q\310\306#\204\276
\324\365K\"\210\353 \210)\202\375
\354L!\204\375
p\355L!\310nopo\203\343
oq\204\352
\310\366\367\217\203\357
\360\370\371\217\210n\203\370
\363p!\210pq\210+\372\306!\210qA@O\373q8N\310\211q\\\310SM\203\254\374 \210\375\376\306\"\203\242\343\377!\211Z\326\327!\203K\201uO\326\373!\306#\206S\324\201v\326\373!I#\202SO\211r@A)B\211[\\B\\Z\227\211Z]\235\204pZ^\235\203\207\201wZ]\"]\201x\201^Z\"\210\202\221\201x\201]Z\"\210\326\327!\204\234OAO\374 \210\202\201y\201z\310\306#\210\374 \210\375\376\306\"\203\346\343\377!\211Q\326\327!\203\334\201uN\326\373!\306#\206\344\324\201{\326\373!I#\202\344N\211r@A)B\211RSBSQ\227Q\373R8\226\201|\232\203kQT\235\204\325QX\235\204QY\235\2037\201wQX\"X\201wQY\"Y\201x\201TQ\"\210\202\325QV\235\203V\201wQV\"V\201x\201WQ\"\210\202\325QW\235\204\325\201x\201VQ\"\210\202\325QT\235\204\325QV\235\204\203QW\235\203\244\201wQV\"V\201wQW\"W\201x\201TQ\"\210\202\325QX\235\203\303\201wQX\"X\201x\201YQ\"\210\202\325QY\235\204\325\201x\201XQ\"\210\326\327!\204\340NAN\374 \210\202\257I\\\237S\237EPBP\202

\201}C!\210\327y\210\323\201~D\306#\210\334 i\374 \210\201\201\200!\203)\201\201\373!\210i`|\210\202ih\201\202B!\203=\201\203B!\210eb\210\323\201\204@\201\205Q\310\306#\204X\324\201\206@\"\210\323\201\207\310\306#\203h\326\327!\204|\201\210\224b\210sj\210\201\211c\210\201\212u\210\201\213u\210\334 e\201\214 \210\310\210e`|\210\201\215\327!\210\201\216c\210^\203\262\201\217c\210s\373_j\210\201\220c\210\334 d\334 e\334 f\334 g\323\201\221\310\306#\203\322\326\327!\204\346\201\210\224b\210sj\210\201\222c\210\201\212u\210\201\213u\210\334 `\201\214 \210\310\210``|\210\201\215\327!\210\201\216c\210W\204Y\203!\201\217c\210s\373_j\210\201\223c\210\334 _\334 `\334 a\334 b\334 cP\237\211P\203^P@@IP@A@\\\373P@8Sfjbkil\\\203\325\\\211r@@)\227Z\\@[ZU\235\204\314Z^\235\203\251\201}e!\210\201\224g\201\225[!\"g\334 e\201x\201UZ\"\210\202\314\201}\201\224fe\"!\210\201\225[!g\334 f\201x\201UZ\"\210\\A\211\\\204cjfU\204\201}\201\224je\"!\210\201\217c\210s\373_j\210\201\226I\201\227\261\210\201}f!\210S\203\363S\211r@@)\227QS@RQU\235\204\352QW\235\203R\201}`!\210\201\224c\201\230R!\"c\334 `\201x\201UQ\"\210\202\352QY\235\203\206\201}\201\224a`\"!\210\201\224c\201\230R!\"c\334 a\201x\201UQ\"\210\202\352QV\235\204\226QX\235\203\302\201}\201\224b\201\224a`\"\"!\210\201\230R!c\334 b\201x\201UQ\"\210\202\352\373R8\226\201\231\232\203\352\201}i!\210\201\232R!\210\334 i\201x\201UQ\"\210SA\211S\204\fkbU\204+\201}\201\224k\201\224`a\"\"!\210\201\217c\210s\373_j\210\201\233I\201\227\261\210\201}b!\210liU\204U\201}l!\210\201\217c\210sj\210\201\234I\201\227\261\210\201}i!\210PA\211P\204>\201}g!\210\201\213u\210dgU\203\207\201\217c\210s\373_j\210\201\235c\210\201\213u\210\201\236c\210\201}c!\210\201\213u\210_cU\203\265\201\217c\210s\373_j\210\201\235c\210\201\213u\210\201\236c\210t\203\352\201}d!\210\201\237dg\327#\210\201\237_c\327#\210\201}h!\210\201\237hi\"\210\201\240\201\241h!!\210\340\201\242!.2\207" [overlay overlay-intangible-list overlay-all-list current-syntax-table case-fold-search vhdl-mode-ext-syntax-table t syntax-table nil set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) re-search-backward "^architecture[ 	\n
\f]+\\w+[ 	\n
\f]+of[ 	\n
\f]+\\(\\w+\\)[ 	\n
\f]+is\\>" re-search-forward error "ERROR:  No architecture found" match-string 1 vhdl-replace-string "." file-name-extension buffer-file-name point-marker "^begin\\>" "^end\\>" vhdl-get-components-package-name message "Wiring components..." "^[ 	]*\\(\\w+\\)[ 	\n
\f]*:[ 	\n
\f]*\\(\\(component[ 	\n
\f]+\\)?\\(\\w+\\)[ 	\n
\f]+\\(--[^\n]*\n[ 	\n
\f]*\\)*\\(\\(generic\\)\\|port\\)[ 	\n
\f]+map\\|\\(\\(entity\\)\\|configuration\\)[ 	\n
\f]+\\(\\(\\w+\\)\\.\\)?\\(\\w+\\)\\([ 	\n
\f]*(\\(\\w+\\))\\)?[ 	\n
\f]+\\(--[^\n]*\n[ 	\n
\f]*\\)*\\(\\(generic\\)\\|port\\)[ 	\n
\f]+map\\)[ 	\n
\f]*(" match-string-no-properties 4 12 7 17 #1="^\\s-*component[ 	\n
\f]+" #2="\\>" #3="ERROR:  Component declaration not found: \"%s\"" vhdl-port-copy file-directory-p find-buffer-visiting (byte-code "\303\205	!q\210\304\305\205	!\210\306\307\310\311 #\210\306\312\313\311 #\210\306\314\313\311 #\210\306\315\316\311 #\210\304\207" [vhdl-use-components-package pack-file-name file-opened create-file-buffer t vhdl-insert-file-contents modify-syntax-entry 45 #4=". 12" syntax-table 10 #5=">" 13 95 #6="w"] 4) ((error (byte-code "\203\304p!\210	q\210\305\306\n\205\"\207" [file-opened source-buffer vhdl-use-components-package pack-file-name kill-buffer error #7="ERROR:  File cannot be opened: \"%s\""] 3))) info (byte-code "\212eb\210\301\302\303Q\304\305#\204\306\307\"\210\310 \210)\304\207" [comp-name re-search-forward #1# #2# nil t error #3# vhdl-port-copy] 4) ((error (byte-code "\203\304p!\210	q\210\305\n\211A@)!\207" [file-opened source-buffer info x kill-buffer error] 3))) kill-buffer #8="^\\s-*entity[ 	\n
\f]+" #9="ERROR:  Entity declaration not found: \"%s\"" (byte-code "\302!q\210\303\304!\210\305\306\307\310 #\210\305\311\312\310 #\210\305\313\312\310 #\210\305\314\315\310 #\210\303\207" [comp-ent-file-name file-opened create-file-buffer t vhdl-insert-file-contents modify-syntax-entry 45 #4# syntax-table 10 #5# 13 95 #6#] 4) ((error (byte-code "\203\303p!\210	q\210\304\305\n\"\207" [file-opened source-buffer comp-ent-file-name kill-buffer error #7#] 3))) (byte-code "\212eb\210\301\302\303Q\304\305#\204\306\307\"\210\310 \210)\304\207" [comp-ent-name re-search-forward #8# "\\>" nil t error #9# vhdl-port-copy] 4) ((error (byte-code "\203\304p!\210	q\210\305\n\211A@)!\207" [file-opened source-buffer info x kill-buffer error] 3))) vhdl-port-flatten 2 vhdl-forward-syntactic-ws vhdl-parse-string "\\(\\(\\w+\\)[ 	\n
\f]*=>[ 	\n
\f]*\\)?\\(\\w+\\),?" 3 ent-name vhdl-entity-file-name ent-file-name arch-decl-pos arch-stat-pos arch-end-pos pack-name vhdl-package-file-name pack-file-name inst-name comp-name comp-ent-name comp-ent-file-name has-generic port-alist generic-alist inst-alist signal-name signal-entry signal-alist local-list written-list single-in-list multi-in-list single-out-list multi-out-list constant-name constant-entry constant-alist single-list multi-list port-beg-pos port-in-pos port-out-pos port-inst-pos port-end-pos generic-beg-pos generic-pos generic-inst-pos generic-end-pos signal-beg-pos signal-pos constant-temp-pos port-temp-pos signal-temp-pos vhdl-use-components-package file-opened visiting-buffer source-buffer vhdl-port-list x vhdl-basic-offset vhdl-auto-align aget "ERROR:  Formal generic \"%s\" mismatch for instance \"%s\"" delete add-to-list vhdl-re-search-forward "\\<port\\s-+map[ 	\n
\f]*(" "ERROR:  Formal port \"%s\" mismatch for instance \"%s\"" "IN" vhdl-goto-marker "^\\s-*-- Internal signal declarations[ 	\n
\f]*-*\n" looking-at "signal\\>" beginning-of-line file-exists-p find-file "^entity[ 	\n
\f]+" "[ 	\n
\f]+is\\>" "ERROR:  Entity not found: \"%s\"" "\\(^\\s-*generic[ 	\n
\f]*(\\)\\|^end\\>" 0 "generic ();\n\n" -4 -1 forward-sexp delete-char "(\n" "\n" "-- global generics\n" "\\(^\\s-*port[ 	\n
\f]*(\\)\\|^end\\>" "port ();\n\n" "-- global ports\n" vhdl-max-marker vhdl-compose-insert-generic "-- generics for \"" "\"\n" vhdl-compose-insert-port "OUT" vhdl-compose-insert-signal "-- ports to \"" "-- outputs of \"" ";" ")" vhdl-align-region-groups switch-to-buffer marker-buffer "Wiring components...done"] 7 (#$ . 500741) nil])
#@38 Insert ENTRY as generic declaration.
(defalias 'vhdl-compose-insert-generic #[(entry) "\304	\305_j\210\n@\306\nA@\261\210\305\n8\203\307\305\n8\261\210\310c\210\311 \2034\312\n8\2034\313\312\n8\314\"\210\315c\210)\207" [pos vhdl-basic-offset entry vhdl-include-port-comments nil 2 " : " " := " ";" point-marker 3 vhdl-comment-insert-inline t "\n"] 3 (#$ . 509843)])
#@35 Insert ENTRY as port declaration.
(defalias 'vhdl-compose-insert-port #[(entry) "\304	\305_j\210\n@\306\305\n8\307\310\n8\311\261\210\312 \203)\313\n8\203)\314\313\n8\315\"\210\316c\210)\207" [pos vhdl-basic-offset entry vhdl-include-port-comments nil 2 " : " " " 3 ";" point-marker 4 vhdl-comment-insert-inline t "\n"] 6 (#$ . 510225)])
#@37 Insert ENTRY as signal declaration.
(defalias 'vhdl-compose-insert-signal #[(entry) "j\210\303	@\304\305	8\306\261\210\n\203\307	8\203\310\307	8\311\"\210\312c\207" [vhdl-basic-offset entry vhdl-include-port-comments "signal " " : " 3 ";" 4 vhdl-comment-insert-inline t "\n"] 5 (#$ . 510576)])
#@105 Generate a package containing component declarations for all entities in the
current project/directory.
(defalias 'vhdl-compose-components-package #[nil "\306 \210\307 \310 \311\n	\312#\313\314\315 !Q\316\f\206
\312#<\317=\320\211>?\321\322	\"\210\323!\203A\324\325\326Q!\204A\327\330!\210\331!\210\332 \210@\203[\333\334A\335Q!\210db\210\202a\336 \210\337c\210\340 \210\341c\210\342 >\341c\210\336 \210\337c\210\343\344!\210	c\210\343\345!\210Bj\210\336 \210\341c\210Bj\210\346c\210Bj\210\336 \210\337c\210Bj\210\342 ?\337c\210\343\347!\210\350\351!\204\263\343\344!\210	\352\261\210@\203\312C\353\232\204\312\354 \210\202\320\336 \210\341c\210<\203]
\355<@8\204\361eb\210\356<@8Sy\210\320\210\357 \210\202/
\360\355<@8!\204/
p\361\355<@8!\320DEFE\203
Eq\204
\320\362\363\217\203!
\364\365\366\217\210D\203*
\367p!\210Fq\210+?b\210\370\312!\210<A\203D
\337c\210Bj\210\342 ?>b\210\371	!\210\342 ><A\211<\204\325eb\210\372 \210\321\373	#.\207" [project pack-name vhdl-package-file-name pack-file-name vhdl-entity-alist default-directory vhdl-require-hierarchy-info vhdl-project-p vhdl-get-components-package-name vhdl-replace-string t "." file-name-extension buffer-file-name aget 0 nil message "Generating components package \"%s\"..." file-exists-p y-or-n-p "File \"" "\" exists; overwrite? " error "ERROR:  Generating components package...aborted" find-file erase-buffer vhdl-template-header "Components package (generated by Emacs VHDL Mode " ")" vhdl-comment-display-line "\n\n" vhdl-template-package-std-logic-1164 "\n" point-marker vhdl-insert-keyword "PACKAGE " " IS\n\n" "-- Component declarations\n" "END " vhdl-standard-p 87 ";\n\n" "" vhdl-template-footer 2 3 vhdl-port-copy file-directory-p find-buffer-visiting (byte-code "\302\303@8!q\210\304\305\303@8!\210\306\307\310\311 #\210\306\312\313\311 #\210\306\314\313\311 #\210\306\315\316\311 #\210\304\207" [ent-alist file-opened create-file-buffer 2 t vhdl-insert-file-contents modify-syntax-entry 45 ". 12" syntax-table 10 ">" 13 95 "w"] 4) ((error (byte-code "\301\302\303\304@8\"\305\"\210\306\207" [ent-alist vhdl-warning format "File cannot be opened: \"%s\"" 2 t nil] 5))) info (byte-code "eb\210\301@8Sy\210\302\210\303 \207" [ent-alist 3 nil vhdl-port-copy] 2) ((error (byte-code "\302\211A@)!\207" [info x vhdl-warning] 3))) kill-buffer vhdl-port-paste-component vhdl-port-paste-context-clause save-buffer "Generating components package \"%s\"...done\n  File created: \"%s\"" ent-alist lazy-lock-minimum-size clause-pos component-pos vhdl-compose-include-header vhdl-version vhdl-basic-offset vhdl-file-footer file-opened visiting-buffer source-buffer] 5 (#$ . 510883) nil])
#@48 Generate block configuration for architecture.
(defalias 'vhdl-compose-configuration-architecture #[(ent-name arch-name ent-alist conf-alist inst-alist &optional insert-conf) "\306 \307 \310\211\211\211\211\211\311\312!\210 \313\261\210!\\\"\203y
\"@\314\f8\203p
\315#\316\f8\203P@\n@\232\203PA\nA\202;\n\203i!Z\211j\210\311\317!\210\nA\211\204Tj\210\203\215!\\\311\312!\210@\313\261\210j\210A\211\204q\311\312!\210\fA@\320\314\f8\313\261\210\321\f8$%\211\203\304$\204\304\322\f8\314@8\232\203\275@@$A\211\204\250\323%$\315#&'\203\361&\203\361!\\j\210\311\324!\210\325 \326&@\261\210\327c\210\202d
\323(\322\f8\315#\211\203d
!\\j\210\311\330!\210\325 \326
@\261\210\331
8\2039
\323\331
8\332\f8\206$
\314
8\315#@\2060
\331
8@A@ \333 \334\261\210\327c\210)\203d
\331
8\203d
!\\j\210\335
@ (%\331\323\331
8 \227\315#8%\210j\210\311\317!\210\316\f8\"A\211\"\204*\n\203\222
!Z\211j\210\311\317!\210\nA\211\204}
!Zj\210#\203\244
\311\317!\202\250
`|.\207" [tmp-alist cons-key inst-prev-path inst-path inst-entry ent-entry current-indentation point-at-bol nil vhdl-insert-keyword "FOR " "\n" 4 t 9 "END FOR;\n" " : " 7 5 aget "USE CONFIGURATION " vhdl-work-library "." ";\n" "USE ENTITY " 3 6 "(" ")" vhdl-compose-configuration-architecture beg margin arch-name vhdl-basic-offset inst-alist insert-conf conf-key conf-alist conf-entry vhdl-compose-configuration-use-subconfiguration ent-alist vhdl-compose-configuration-hierarchical] 11 (#$ . 513603)])
#@37 Generate configuration declaration.
(defalias 'vhdl-compose-configuration #[(&optional ent-name arch-name) "\306 \210\307\310 \206	\311#\307\n\310 \206	\311#\312\211\211\211@ABCD\311\313 \312\211\211EFGHI\314J!\210\315\316!\203z\316 G\317G@GA\"\211G\203zG@E\320\321E!>\203qEFBF\322E\320\312#\210GA\211G\204U\323\216\204\250\212\324\325\312\311#\203\243\326\327!\226\330\232\204\243\331\332!\211\203\243\331\333!\211K\204\247\334\335!\210)\336L\337KQ\"@\332\307\332\307D\227\311#8K\227\311#8A.\340\341@\"\210M\203
\336N@\311#\342\343\344 !Q\345
!\203\364\346\347
\350Q!\204\364\334\351!\210\352
!\210\353 \210\354\312!\210O\203
\355\356\357K\360\260!\210db\210\2024
\361 \210\362c\210\2024
B\2044
\363\364\312\"\210\312\210\362c\210\361 \210\362c\210`\365\366 \312\"\210\f`U\204E
\362c\210\367\370!\210@c\210\367\371!\210c\210\367\372!\210Pj\210\373KDCA\311&\210\367\374!\210@\375\261\210
\203\232
\362c\210O\203\215
Q\376\232\204\215
\377 \210\202\225
\361 \210\201Rc\210\201S \210\340\201T\201U\201V@\"
\205\263
\201U\201W
\"P\".\207" [vhdl-entity-alist default-directory vhdl-config-alist ent-name pos conf-file-name vhdl-require-hierarchy-info aget vhdl-project-p t nil syntax-table set-syntax-table fboundp overlay-lists append intangible overlay-properties overlay-put ((byte-code "\302!\210\303\304!\203	\203\305	@\306\307#\210	A\211\204\302\207" [current-syntax-table overlay-intangible-list set-syntax-table fboundp overlay-lists overlay-put intangible t] 5)) re-search-backward "^\\(architecture\\s-+\\(\\w+\\)\\s-+of\\s-+\\(\\w+\\)\\|end\\)\\>" match-string 1 "END" match-string-no-properties 3 2 error "ERROR:  Not within an architecture" vhdl-replace-string " " message "Generating configuration \"%s\"..." "." file-name-extension buffer-file-name file-exists-p y-or-n-p "File \"" "\" exists; overwrite? " "ERROR:  Creating configuration...aborted" find-file erase-buffer set-buffer-modified-p vhdl-template-header "Configuration declaration for design \"" "(" ")\"" vhdl-comment-display-line "\n\n" re-search-forward "^end\\>" vhdl-template-standard-package vhdl-work-library vhdl-insert-keyword "CONFIGURATION " " OF " " IS\n" vhdl-compose-configuration-architecture "END " ";" "" vhdl-template-footer conf-name inst-alist from-speedbar conf-alist ent-alist overlay overlay-intangible-list overlay-all-list current-syntax-table case-fold-search vhdl-mode-ext-syntax-table arch-name vhdl-compose-configuration-name vhdl-compose-configuration-create-file vhdl-configuration-file-name vhdl-compose-include-header vhdl-basic-offset vhdl-file-footer "\n" save-buffer "%s" format "Generating configuration \"%s\"...done" "\n  File created: \"%s\""] 8 (#$ . 515171) nil])
#@53 String appended to compile command after file name.
(defvar vhdl-compile-post-command "" (#$ . 517955))
#@99 Return the Makefile name of the current project or the current compiler if
no project is defined.
(defalias 'vhdl-makefile-name #[nil "\306	\"\306\n\"\307\310\311
8\206\311\f8B\312\f8\313\314
8Q\"*\207" [vhdl-project-alist vhdl-project vhdl-compiler-alist vhdl-compiler compiler-alist project-alist aget vhdl-replace-string "\\(.*\\)\n\\(.*\\)" 8 9 "\n" 6] 6 (#$ . 518065)])
#@60 Return the directory where compilation/make should be run.
(defalias 'vhdl-compile-directory #[nil "\306\307\310!\"\306\n\"\311	\203\312\313\314	8B\315\f8\"\202!\316\f8!\317\320
!\203.
\2023\321
\322 \"!+\207" [vhdl-project-alist project vhdl-compiler-alist vhdl-compiler compiler directory aget vhdl-project-p t vhdl-resolve-env-variable vhdl-replace-string "\\(.*\\)" 5 9 6 file-name-as-directory file-name-absolute-p expand-file-name vhdl-default-directory] 5 (#$ . 518452)])
#@41 Remove duplicate elements from IN-LIST.
(defalias 'vhdl-uniquify #[(in-list) "\302	\203\303\300	@\"\210	A\211\204)\207" [out-list in-list nil add-to-list] 4 (#$ . 518947)])
#@31 Set current compiler to NAME.
(defalias 'vhdl-set-compiler #[(name) "\303	\"\203\304\305\n\"\207\306\307\310\"!\207" [name vhdl-compiler-alist vhdl-compiler assoc message "Current compiler: \"%s\"" vhdl-warning format "Unknown compiler: \"%s\""] 4 (#$ . 519133) (list (let ((completion-ignore-case t)) (completing-read "Compiler name: " vhdl-compiler-alist nil t)))])
#@29 Initialize for compilation.
(defalias 'vhdl-compile-init #[nil "\203\306\307	@8@\"?\205\207	\310\211\211\203M\307\f@8\211@\311\232\204F\306\n@\"\204F\n@\nA@\312U?\205<\nA@\313\n8\314\n8FB\fA\211\204\315\237\"+	\310\211\316\f\203\317\f@8\211@\311\232\204x\306\n@\"\204x\nB\fA\211\204`\315
\237\"\211+\207" [compilation-error-regexp-alist vhdl-compiler-alist sublist regexp-alist commands-alist compilation-file-regexp-alist assoc 11 nil "" 0 2 3 append (("^Compiling \"\\(.+\\)\"" 1)) 12] 6 (#$ . 519513)])
#@30 Name of file to be compiled.
(defvar vhdl-compile-file-name nil (#$ . 520063))
#@105 Function called within `compile' to print out file name for compilers that
do not print any file names.
(defalias 'vhdl-compile-print-file-name #[nil "\301\302\261\207" [vhdl-compile-file-name "Compiling \"" "\"\n"] 3 (#$ . 520149)])
#@70 Get compiler options.  Returning nil means do not compile this file.
(defalias 'vhdl-get-compile-options #[(project compiler file-name &optional file-options-only) "A@\306\307\n8\"\211@\205\310\f8\311 \312\211\203?\313\211@@)\"\204?A\211\204'\205M\211@A)??\205\237\203_\204_\314\202\237\211@A)\315\316	B\"
\203\200\315\317
B\320	Q\"\203\225\315\321B\320	\320
\260\"\206\237
\206\237	.\207" [compiler compiler-options project vhdl-compiler project-entry project-options aget 4 2 vhdl-work-library nil string-match default vhdl-replace-string "\\(.*\\)" "\\(.*\\)\n\\(.*\\)" "\n" "\\(.*\\)\n\\(.*\\)\n\\(.*\\)" file-name exception-list work-library case-fold-search file-options x file-options-only] 8 (#$ . 520391)])
#@19 Get make options.
(defalias 'vhdl-get-make-options #[(project compiler) "\3068\307\310\n8\"\211A@\311 \312\313\3068B\"
\203,\312\314
B\315	Q\"
\2061	,\207" [compiler compiler-options project vhdl-compiler project-entry project-options 3 aget 4 vhdl-makefile-name vhdl-replace-string "\\(.*\\)" "\\(.*\\)\n\\(.*\\)" "\n" makefile-name] 6 (#$ . 521188)])
#@78 Compile current buffer using the VHDL compiler specified in
`vhdl-compiler'.
(defalias 'vhdl-compile #[nil "\306 \210\307	\"\307\f\310#\206\311\312\f\"\211@\313 \203'\314 \202+\315\314 !\316\n
# \310!\317!\204E\311\320\"\210\321\322\"\203T\323\323Q\203^\314 \202b\315\314 !\"\324
8A@\325U\203{\326
8A@\325U\203{\327! \203\240\205\243\330\322 \322#\331\232?\205\232\322#P\260!\202\243\332\333!.\207" [vhdl-project-alist vhdl-project project vhdl-compiler-alist vhdl-compiler compiler vhdl-compile-init aget nil error "ERROR:  No such compiler: \"%s\"" vhdl-compile-directory buffer-file-name file-relative-name vhdl-get-compile-options file-directory-p "ERROR:  Compile directory does not exist: \"%s\"" string-match " " "\"" 10 0 11 vhdl-compile-print-file-name compile "" vhdl-warning "Your project settings tell me not to compile this file" command default-directory vhdl-compile-absolute-path file-name options compilation-process-setup-function vhdl-compile-file-name vhdl-compile-post-command] 9 (#$ . 521563) nil])
#@41 Default target for `vhdl-make' command.
(defvar vhdl-make-target "all" (#$ . 522646))
#@164 Call make command for compilation of all updated source files (requires
`Makefile').  Optional argument TARGET allows to compile the design
specified by a target.
(defalias 'vhdl-make #[(&optional target) "\206	\306\307	\n#\310 \210\311\f\"\311\"\206 \312\313\"\3148\315
\"\316 \317!\204@\312\320\"\210\321\322\232\203L\323\202N\324\324	\260!-\207" [target vhdl-make-target vhdl-minibuffer-local-map vhdl-project-alist vhdl-project project read-from-minibuffer "Target: " vhdl-compile-init aget error "ERROR:  No such compiler: \"%s\"" 2 vhdl-get-make-options vhdl-compile-directory file-directory-p "ERROR:  Compile directory does not exist: \"%s\"" compile "" "make" " " vhdl-compiler-alist vhdl-compiler compiler command options default-directory] 6 (#$ . 522739) nil])
#@22 Generate `Makefile'.
(defalias 'vhdl-generate-makefile #[nil "\305	\"\206\306\307	\"\310\n8\211\203(\311 \312\313\314B\315 \316\317 Q\"!)\202*\320 *\207" [vhdl-compiler-alist vhdl-compiler compiler command default-directory aget error "ERROR:  No such compiler: \"%s\"" 4 vhdl-compile-directory compile vhdl-replace-string "\\(.*\\) \\(.*\\)" vhdl-makefile-name " " vhdl-work-library vhdl-generate-makefile-1] 7 (#$ . 523556) nil])
#@58 Get packages from LIB-ALIST that belong to WORK-LIBRARY.
(defalias 'vhdl-get-packages #[(lib-alist work-library) "\304	\203#	\211@@)\227\227\232\203	\211@A)B	A\211\204)\207" [pack-list lib-alist x work-library nil] 3 (#$ . 524003)])
#@53 Generate Makefile for current project or directory.
(defalias 'vhdl-generate-makefile-1 #[nil "\306 \203\307	\"\204/\310!\204/\311!\210\202/\312\n!\307	\"\204.\310!\204.\313!\210)\312\314 !\306 \315
\f\206>\316#@\315A\f\206J\316#B\315C\f\206V\316#D\317\315EF\"8G\320G@BH\321GA@BI\320\322G8BJ\320\323G8BK\320\324G8BL\325G8M\326 \227N\327\330 \n\"O\331 P\332\211'Q\332\211RS\332\211TU\332\211VW\332\211XY\332\211Z[\332\211\\]\332\211^_\332\211`a\332\211bc\332\211de\332\211fg\332\211hi\332\211jk\332\211lm\332\211no\332\211pq\333O!\204
\334O\316\"\210G\204
\335\336F\"\210\337\340P\"\210@p@\203\227@@\211f@]\322f8\203\216\341\322f8O\"^\324f8Q\342f8Y\315'^\"\211q@SqA@T\332\211WX\343HM]!\"o]oBUBU]SBS\344YN\"[\345T[\"T[\\\346\347^STD#\210Q\203~Q@\211g@_]\350_Qa\341\322g8O\"`\324g8R\325g8Y\315'`\"\211q@SqA@T\343IM_\351]Q!\"oaoBUBUaWBWaSBS]TBTR\203RR@j\352j8\203/\352j8\227N\232\203I\353j8\206:\325j8\211mTBTmXBXRA\211R\204\344YN\"[\345T[\"T\345\\[\"\\\346\347`STD#\210QA\211Q\204\254
]W\345X\\\"EVBV@A\211@\204.
p@BpB\203\222B@\211h@b\341\322h8O\"c\324h8]\325h8_\342h8R\353h8Y\315'c\"\211q@SqA@T]CX\343JMb!\"oboBUBUbSBS]\211\350_QTBBT\344YN\"[\345T[\"TR\203oR@j\322j8m\324j8n\325j8\227N\232\203fm\203SmTBTmXBXn\203fnTBTnXBXRA\211R\204$\346\347cSTD#\210b\332\345X[\"EVBVBA\211B\204\244pBDpD\203\237D@\211i@d\332k\322i8\203\226\341\322i8O\"e\342i8Y\354i8Z\315'e\"\211q@SqA@T\343KMd!\"odoBUBUdSBS\344YN\"[\345T[\"T[\\\346\347eSTD#\210\353i8\203\204d\355Pk\341\353i8O\"l\315'l\"\211q@SqA@T\343LMd!\"okoBUBUkSBSdTBT\344ZN\"[\345T[\"T\345\\[\"\\\346\347lSTD#\210dk\205\216kC\\EVBVDA\211D\204\237pD\315r\f\"\315EF\"s\356s8t\357\343\320\353\f8\206\304\353s8Bt\"!u\327PO\"vpw\332\211xW\332\211Xy\332\211z{\360U!U\360V!V'\211p\203p\211|@A)\211x\361x@\362\"\240\210pA\211p\204\374\361'\363\"'\364v\316\211#q\210\365 \210\366\367\370P!\371}\372\261\210\f\203D\373\f@\261\210\202J\374\375\261\210\376F\377\201\200\201\201!\201\202 \372\261\210\201\203\201\204s@\201\205\201\206\fs\332#~\201\207\232\203\200\201\207\202\206\201\210~P\372\261\210\201\211\201\212u!\203\233u\202\244\341\327u\"O\"!u\201\213\201\214N\201\215u\372\261\210\201\216c\210UpU\203\360\201\217N\350U\211|@@)\201\220N\201\221U\211|@A)\261\210UA\211U\204\306\201\222\201\223\261\210p\211U\203!\201\224\201\225N\350U\211|@@)\201\226\261\210UA\211U\204
\372c\210pU\201\227\372@\201\230\201\231\3228\201\232\261\210\201\233\372A@\201\234\201\235\261\210\201\236\372\3228\201\230\201\237N\201\240\201\241N\201\242\201\243\343\201\244\325s8B\201\245N\201\240\326 R\"\372\261
\210\201\246@\351A@\351\3228\372\261\210\201\247c\210V\203h\361V@A@\362\"W\361\201\250\322V@8!\362\"XV\211|@@)z\315@z\316#@\206\345\315Bz\316#@\206\345\315Dz\316#@{\372z\261\210z{\232\204\375\201\251{\261\210\201\230\201\231\3228\201\252N\350z\201\226\261\210W\2032\201\252N\350W@\201\226\261\210WA\211W\204X\203\\\307X@U\"\203SzX@\232\204S\201\231X@\261\210XA\211X\2047\372c\210VA\211V\204\245\201\253c\210'\203x'@q\201\206\fsq@\316$yqA@S\361\201\250\322q8!\362\"TSpS\203\307\201\254N\350S@\201\226SA\203\270\201\255\202\273\201\230\261\210SA\211S\204\240pS\201\231q@\261\210T\203T@S\235\204\376\307T@U\"\203\376\201\231\201\225N\350T@\201\226\261\210TA\211T\204\331y\203=\201\256y\201\257=\203\201\260\202 y\351q@~\201\207\232\2033\201\207\2026\201\261\372\261\210\202oSpS\203k\201\262N\350S@\201\226SA\203^\201\255\202_\372\261\210SA\211S\204FpS'A\211'\204r\201\263P\201\264\261\210\201\265\201\266!\210\337\201\267P\"\210\201\270v!\203\267\201\271 \210\201\272p!\210wq\210\201\273\201\274v\"\202\314\201\275\201\276\201\277\312v!\"!\210\201\300p!.=\207" [vhdl-project vhdl-file-alist default-directory directory project vhdl-entity-alist vhdl-project-p assoc vhdl-load-cache vhdl-scan-project-contents abbreviate-file-name vhdl-scan-directory-contents vhdl-default-directory aget t 12 "\\(.*\\)" "\\(.*\\) \\(.*\\)" 2 3 4 5 vhdl-work-library expand-file-name vhdl-compile-directory vhdl-makefile-name nil file-exists-p make-directory error "Please contact the VHDL Mode maintainer for support of \"%s\"" message "Generating makefile \"%s\"..." file-relative-name 6 vhdl-replace-string vhdl-get-packages append aput rule-alist "-" " " 8 7 10 "-body" 9 vhdl-resolve-env-variable vhdl-sort-alist sort string< #[(a b) "\211A@)@\n\211A@)@\231\207" [a x b] 3] find-file-noselect erase-buffer "# -*- Makefile -*-\n" "### " file-name-nondirectory " - VHDL Makefile generated by Emacs VHDL Mode " "\n" "\n# Project   : " "\n# Directory : \"" "\"" "\n# Platform  : " "\n# Generated : " ent-alist vhdl-config-alist conf-alist vhdl-package-alist pack-alist vhdl-compiler-alist vhdl-compiler regexp-list ent-regexp arch-regexp conf-regexp pack-regexp pack-body-regexp adjust-case work-library compile-directory makefile-name arch-alist inst-alist target-list depend-list unit-list prim-list second-list subcomp-list lib-alist lib-body-alist pack-list all-pack-list ent-key ent-file-name arch-key arch-file-name ent-arch-key conf-key conf-file-name pack-key pack-file-name ent-entry arch-entry conf-entry pack-entry inst-entry pack-body-key pack-body-file-name inst-ent-key inst-conf-key tmp-key tmp-list rule vhdl-project-alist compiler compiler-id library-directory makefile-path-name orig-buffer cell options unit-key unit-name x vhdl-version vhdl-compile-post-command vhdl-makefile-default-targets format-time-string "%Y-%m-%d %T " user-login-name "\n\n# Define compilation command and options\n" "\nCOMPILE = " "\nOPTIONS = " vhdl-get-compile-options "" "\nPOST-COMPILE = " directory-file-name file-name-absolute-p "\n\n# Define library paths\n" "\nLIBRARY-" " = " "\n\n# Define library unit files\n" "\nUNIT-" " = \\\n	$(LIBRARY-" ")/" "\n\n\n# Define list of all library unit files\n" "\nALL_UNITS =" " \\\n	" "$(UNIT-" ")" "\n\n\n# Rule for compiling entire design\n" " :" " \\\n		" " \\\n		$(ALL_UNITS)\n" "\n\n# Rule for cleaning entire design\n" " : " "\n	-rm -f $(ALL_UNITS)\n" "\n\n# Rule for creating library directory\n" " \\\n		$(LIBRARY-" ")\n" "\n$(LIBRARY-" ") :" "\n	" "\\(.*\\)\n\\(.*\\)" "$(LIBRARY-" "\n\n.PHONY : " "\n\n# Rules for compiling single library units and their subhierarchy\n" vhdl-uniquify " \\\n" " \\\n		$(UNIT-" "\n\n# Rules for compiling single library unit files\n" "\n$(UNIT-" " \\" "\n	$(COMPILE) " default "$(OPTIONS)" " $(POST-COMPILE)" "\n	@touch $(UNIT-" "\n\n### " " ends here\n" run-hooks vhdl-makefile-generation-hook "Generating makefile \"%s\"...done" file-writable-p save-buffer kill-buffer add-to-history file-name-history vhdl-warning-when-idle format "File not writable: \"%s\"" switch-to-buffer] 18 (#$ . 524255)])
#@36 Address for VHDL Mode bug reports.
(defconst vhdl-mode-help-address "Reto Zimmermann <reto@gnu.org>" (#$ . 531594))
#@44 Submit via mail a bug report on VHDL Mode.
(defalias 'vhdl-submit-bug-report #[nil "\303\304!\205
\305\306	\307\nP\310\311\312\313\314\315\316\317\320\321\322\323\324\325\326\327\330\331\332\333\334\335\336\337\340\341\342\343\344\345\346\347\350\351\352\353\354\355\356\357\360\361\362\363\364\365\366\367\370\371\372\373\374\375\376\377\201@\201A\201B\201C\201D\201E\201F\201G\201H\201I\201J\201K\201L\201M\201N\201O\201P\201Q\201R\201S\201T\201U\201V\201W\201X\201Y\201Z\201[\201\\\201]\201^\201_\201`\201a\201b\201c\201d\201e\201f\201g\201h\201i\201j\201k\201l\201m\201n\201o\201p\201q\201r\201s\201t\201u\201v\201w\201x\201y\201z\201{\201|\201}\201~\201\201\200\257y\201\201\201\202\201\203&)\207" [reporter-prompt-for-summary-p vhdl-mode-help-address vhdl-version y-or-n-p "Do you want to submit a report on VHDL Mode? " t reporter-submit-bug-report "VHDL Mode " vhdl-offsets-alist vhdl-comment-only-line-offset tab-width vhdl-electric-mode vhdl-stutter-mode vhdl-indent-tabs-mode vhdl-project-alist vhdl-project vhdl-project-file-name vhdl-project-auto-load vhdl-project-sort vhdl-compiler-alist vhdl-compiler vhdl-compile-use-local-error-regexp vhdl-makefile-default-targets vhdl-makefile-generation-hook vhdl-default-library vhdl-standard vhdl-basic-offset vhdl-upper-case-keywords vhdl-upper-case-types vhdl-upper-case-attributes vhdl-upper-case-enum-values vhdl-upper-case-constants vhdl-use-direct-instantiation vhdl-array-index-record-field-in-sensitivity-list vhdl-compose-configuration-name vhdl-entity-file-name vhdl-architecture-file-name vhdl-configuration-file-name vhdl-package-file-name vhdl-file-name-case vhdl-electric-keywords vhdl-optional-labels vhdl-insert-empty-lines vhdl-argument-list-indent vhdl-association-list-with-formals vhdl-conditions-in-parenthesis vhdl-zero-string vhdl-one-string vhdl-file-header vhdl-file-footer vhdl-company-name vhdl-copyright-string vhdl-platform-spec vhdl-date-format vhdl-modify-date-prefix-string vhdl-modify-date-on-saving vhdl-reset-kind vhdl-reset-active-high vhdl-clock-rising-edge vhdl-clock-edge-condition vhdl-clock-name vhdl-reset-name vhdl-model-alist vhdl-include-port-comments vhdl-include-direction-comments vhdl-include-type-comments vhdl-include-group-comments vhdl-actual-port-name vhdl-instance-name vhdl-testbench-entity-name vhdl-testbench-architecture-name vhdl-testbench-configuration-name vhdl-testbench-dut-name vhdl-testbench-include-header vhdl-testbench-declarations vhdl-testbench-statements vhdl-testbench-initialize-signals vhdl-testbench-include-library vhdl-testbench-include-configuration vhdl-testbench-create-files vhdl-testbench-entity-file-name vhdl-testbench-architecture-file-name vhdl-compose-create-files vhdl-compose-configuration-create-file vhdl-compose-configuration-hierarchical vhdl-compose-configuration-use-subconfiguration vhdl-compose-include-header vhdl-compose-architecture-name vhdl-components-package-name vhdl-use-components-package vhdl-self-insert-comments vhdl-prompt-for-comments vhdl-inline-comment-column vhdl-end-comment-column vhdl-auto-align vhdl-align-groups vhdl-align-group-separate vhdl-align-same-indent vhdl-highlight-keywords vhdl-highlight-names vhdl-highlight-special-words vhdl-highlight-forbidden-words vhdl-highlight-verilog-keywords vhdl-highlight-translate-off vhdl-highlight-case-sensitive vhdl-special-syntax-alist vhdl-forbidden-words vhdl-forbidden-syntax vhdl-directive-keywords vhdl-speedbar-auto-open vhdl-speedbar-display-mode vhdl-speedbar-scan-limit vhdl-speedbar-jump-to-unit vhdl-speedbar-update-on-saving vhdl-speedbar-save-cache vhdl-speedbar-cache-file-name vhdl-index-menu vhdl-source-file-menu vhdl-hideshow-menu vhdl-hide-all-init vhdl-print-two-column vhdl-print-customize-faces vhdl-intelligent-tab vhdl-indent-syntax-based vhdl-indent-comment-like-next-code-line vhdl-word-completion-case-sensitive vhdl-word-completion-in-minibuffer vhdl-underscore-is-part-of-word vhdl-mode-hook #[nil "\203\301\302\303\304\"\305\306\260\202\307c\207" [vhdl-special-indent-hook "\n@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\n" "vhdl-special-indent-hook is set to '" format "%s" ".\nPerhaps this is your problem?\n" "@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\n\n" "\n"] 5] nil "Hi Reto,"] 124 (#$ . 531716) nil])
#@1572 Release Notes for VHDL Mode 3.33
================================

  - New Features
  - User Options


New Features
------------

CONFIGURATION DECLARATION GENERATION:
  - Automatic generation of a configuration declaration for a design.
    (See documentation (`C-c C-h') in section on STRUCTURAL COMPOSITION.)


Key Bindings
------------

For Emacs compliance the following key bindings have been changed:

- `C-c c'        ->  `C-c C-c'      `vhdl-comment-uncomment-region'
- `C-c f'        ->  `C-c C-i C-f'  `vhdl-fontify-buffer'
- `C-c s'        ->  `C-c C-i C-s'  `vhdl-statistics-buffer'
- `C-c C-c ...'  ->  `C-c C-m ...'  `vhdl-compose-...'


User Options
------------

`vhdl-configuration-file-name': (new)
  Specify how the configuration file name is obtained.
`vhdl-compose-configuration-name': (new)
  Specify how the configuration name is obtained.
`vhdl-compose-configuration-create-file': (new)
  Specify whether a new file should be created for a configuration.
`vhdl-compose-configuration-hierarchical': (new)
  Specify whether hierarchical configurations should be created.
`vhdl-compose-configuration-use-subconfiguration': (new)
  Specify whether subconfigurations should be used inside configurations.
`vhdl-makefile-default-targets': (new)
  Customize names of Makefile default targets.
`vhdl-indent-comment-like-next-code-line': (new)
  Specify whether comment lines are indented like following code line.
`vhdl-array-index-record-field-in-sensitivity-list': (new)
  Specify whether to include array indices / record fields in sensitivity list.

(defconst vhdl-doc-release-notes nil (#$ . 536046))
#@1101 Reserved words in VHDL
----------------------

VHDL'93/02 (IEEE Std 1076-1993/2002):
  `vhdl-02-keywords'      : keywords
  `vhdl-02-types'         : standardized types
  `vhdl-02-attributes'    : standardized attributes
  `vhdl-02-enum-values'   : standardized enumeration values
  `vhdl-02-functions'     : standardized functions
  `vhdl-02-packages'      : standardized packages and libraries

VHDL-AMS (IEEE Std 1076.1 / 1076.1.1):
  `vhdl-ams-keywords'     : keywords
  `vhdl-ams-types'        : standardized types
  `vhdl-ams-attributes'   : standardized attributes
  `vhdl-ams-enum-values'  : standardized enumeration values
  `vhdl-ams-constants'    : standardized constants
  `vhdl-ams-functions'    : standardized functions

Math Packages (IEEE Std 1076.2):
  `vhdl-math-types'       : standardized types
  `vhdl-math-constants'   : standardized constants
  `vhdl-math-functions'   : standardized functions
  `vhdl-math-packages'    : standardized packages

Forbidden words:
  `vhdl-verilog-keywords' : Verilog reserved words

NOTE: click `mouse-2' on variable names above (not in XEmacs).
(defconst vhdl-doc-keywords nil (#$ . 537677))
#@644 For VHDL coding style and naming convention guidelines, see the following
references:

[1] Ben Cohen.
    "VHDL Coding Styles and Methodologies".
    Kluwer Academic Publishers, 1999.
    http://members.aol.com/vhdlcohen/vhdl/

[2] Michael Keating and Pierre Bricaud.
    "Reuse Methodology Manual, Second Edition".
    Kluwer Academic Publishers, 1999.
    http://www.openmore.com/openmore/rmm2.html

[3] European Space Agency.
    "VHDL Modelling Guidelines".
    ftp://ftp.estec.esa.nl/pub/vhdl/doc/ModelGuide.{pdf,ps}

Use user options `vhdl-highlight-special-words' and `vhdl-special-syntax-alist'
to visually support naming conventions.
(defconst vhdl-doc-coding-style nil (#$ . 538831))
#@58 Echo the current version of VHDL Mode in the minibuffer.
(defalias 'vhdl-version #[nil "\302\303	#\210\304 \207" [vhdl-version vhdl-time-stamp message "VHDL Mode %s (%s)" vhdl-keep-region-active] 4 (#$ . 539531) nil])
#@52 Display VARIABLE's documentation in *Help* buffer.
(defalias 'vhdl-doc-variable #[(variable) "\306\307D\310\311!\"\210	r\312\313\314!\203\314 \202\315!q\210p\316 \210\n\317\211\320\211\320\321 \210\322\323!\210+\211\324\325\326\"!\210rq\210\327 \210)\330 \331!\210+\207" [variable default-directory #1=#:old-dir buffer-read-only buffer-file-name buffer-undo-list help-setup-xref vhdl-doc-variable called-interactively-p interactive get-buffer-create fboundp help-buffer "*Help*" kill-all-local-variables nil t erase-buffer run-hooks temp-buffer-setup-hook princ documentation-property variable-documentation help-mode help-print-return-message internal-temp-output-buffer-show inhibit-modification-hooks inhibit-read-only #2=#:buf standard-output] 5 (#$ . 539756) nil])
#@51 Display VHDL Mode documentation in *Help* buffer.
(defalias 'vhdl-doc-mode #[nil "\306\307C\310\311!\"\210r\312\313\314!\203\314 \202\315!q\210p\316 \210	\317\211\320\211\320\321 \210\322\323!\210+\211\324!\210\324\325!\210\324\326\327!!\210rq\210\330 \210)\331 \332!\210+\207" [default-directory #1=#:old-dir buffer-read-only buffer-file-name buffer-undo-list inhibit-modification-hooks help-setup-xref vhdl-doc-mode called-interactively-p interactive get-buffer-create fboundp help-buffer "*Help*" kill-all-local-variables nil t erase-buffer run-hooks temp-buffer-setup-hook princ " mode:\n" documentation vhdl-mode help-mode help-print-return-message internal-temp-output-buffer-show inhibit-read-only #2=#:buf standard-output mode-name] 5 (#$ . 540555) nil])
(provide 'vhdl-mode)